AS7C3364PFS32B datasheet, PDF - EEWORLD Datasheet

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AS7C3364PFS32B: Description3.3V 64K X 32/36 pipeline burst synchronous SRAM; File Size531KB，19 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C3364PFS32B Overview

3.3V 64K X 32/36 pipeline burst synchronous SRAM

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December 2004

AS7C3364PFS32B

AS7C3364PFS36B

3.3V 64K X 32/36 pipeline burst synchronous SRAM

Features

•

Organization: 65,536 words × 32 or 36 bits

Fast clock speeds to 200 MHz

Fast clock to data access: 3.0/3.5/4.0 ns

Fast OE access time: 3.0/3.5/4.0 ns

Fully synchronous register-to-register operation

Single-cycle deselect

Asynchronous output enable control

Available in 100-pin TQFP package

•

Linear or interleaved burst control

Individual byte write and global write

Snooze mode for reduced power-standby

Common data inputs and data outputs

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[15:0]

CLK

CLR

Address

CLK

Burst logic

64K × 32/36

Memory

array

GWE

BWE

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

Power

down

Enable

delay

CLK

36/32

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

36/32

DQ [a:d]

Selection guide

–200

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

200

3.0

375

130

–166

166

3.5

350

100

–133

7.5

133

325

Units

MHz

12/10/04; v.1.4

Alliance Semiconductor

P. 1 of 19

AS7C3364PFS32B

AS7C3364PFS36B

Functional description

The AS7C3364PFS32B and AS7C3364PFS36B are high-performance CMOS 2-Mbit synchronous Static Random Access

Memory (SRAM) devices organized as 65,536 words × 32 or 36 bits, and incorporate a two-stage register-register pipeline for

highest frequency on any given technology.

Timing for these devices is compatible with existing Pentium

synchronous cache specifications. This architecture is suited

for ASIC, DSP and PowerPC

™1

-based systems in computing, datacom, instrumentation, and telecommunications systems.

Fast cycle times of 5.0/6.0/7.5 ns with clock access times (t

) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus

frequencies. Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the

controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent

internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip

address register when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In

a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are

carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock

edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next

access of the burst when ADV is sampled Low, and both address strobes are High. Burst mode is selectable with the LBO

input. With LBO unconnected or driven High, burst operations use a Pentium

count sequence. With LBO driven LOW, the

device uses a linear count sequence suitable for PowerPC

™

and many other applications.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable

GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is High, one or more

bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are

disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled

Low. Address is incremented internally to the next burst address if BWn and ADV are sampled Low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC

and ADSP are as follows:

• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP High).

• Master chip enable CE0 blocks ADSP, but not ADSC.

AS7C3364PFS32B and AS7C3364PFS36B family operates from a core 3.3V power supply. I/Os use a separate power supply

that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.

TQFP capacitance

Parameter

Input capacitance

I/O capacitance

* Guaranteed not tested

Symbol

IN*

I/O*

Test conditions

= 0V

OUT

= 0V

Min

Max

Unit

TQFP thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

1–layer

Test conditions follow standard test methods and

procedures for measuring thermal impedance,

per EIA/JESD51

4–layer

Symbol

Typical

Units

°C/W

1 PowerPC

™

is a trademark International Business Machines Corporation.

12/10/04; v.1.4

Alliance Semiconductor

P. 4 of 19

AS7C3364PFS32B Related Products

	AS7C3364PFS32B	AS7C3364PFS32B-133TQC	AS7C3364PFS32B-133TQI	AS7C3364PFS32B-166TQC	AS7C3364PFS32B-166TQCN
Description	3.3V 64K X 32/36 pipeline burst synchronous SRAM	3.3V 64K X 32/36 pipeline burst synchronous SRAM	3.3V 64K X 32/36 pipeline burst synchronous SRAM	3.3V 64K X 32/36 pipeline burst synchronous SRAM	3.3V 64K X 32/36 pipeline burst synchronous SRAM
Is it Rohs certified?	-	incompatible	incompatible	incompatible	conform to
Maker	-	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	-	QFP	QFP	QFP	QFP
package instruction	-	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87	LQFP, QFP100,.63X.87
Contacts	-	100	100	100	100
Reach Compliance Code	-	unknow	unknow	unknow	unknow
ECCN code	-	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	-	4 ns	4 ns	3.5 ns	3.5 ns
Other features	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	-	133 MHz	133 MHz	166 MHz	166 MHz
I/O type	-	COMMON	COMMON	COMMON	COMMON
JESD-30 code	-	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
JESD-609 code	-	e0	e0	e0	e3
length	-	20 mm	20 mm	20 mm	20 mm
memory density	-	2097152 bi	2097152 bi	2097152 bi	2097152 bi
Memory IC Type	-	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	-	32	32	32	32
Number of functions	-	1	1	1	1
Number of terminals	-	100	100	100	100
word count	-	65536 words	65536 words	65536 words	65536 words
character code	-	64000	64000	64000	64000
Operating mode	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	-	70 °C	85 °C	70 °C	70 °C
organize	-	64KX32	64KX32	64KX32	64KX32
Output characteristics	-	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	LQFP	LQFP	LQFP	LQFP
Encapsulate equivalent code	-	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87	QFP100,.63X.87
Package shape	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Parallel/Serial	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	245
power supply	-	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	-	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum standby current	-	0.03 A	0.03 A	0.03 A	0.03 A
Minimum standby current	-	3.14 V	3.14 V	3.14 V	3.14 V
Maximum slew rate	-	0.325 mA	0.325 mA	0.35 mA	0.35 mA
Maximum supply voltage (Vsup)	-	3.465 V	3.465 V	3.465 V	3.465 V
Minimum supply voltage (Vsup)	-	3.135 V	3.135 V	3.135 V	3.135 V
Nominal supply voltage (Vsup)	-	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	-	YES	YES	YES	YES
technology	-	CMOS	CMOS	CMOS	CMOS
Temperature level	-	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	MATTE TIN
Terminal form	-	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	-	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	30
width	-	14 mm	14 mm	14 mm	14 mm

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