L-FW322-07-NV100-DT datasheet, PDF

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L-FW322-07-NV100-DT: DescriptionSerial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA100, ROHS COMPLIANT, FSBGA-100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，2 Pages; ManufacturerBroadcom; Environmental Compliance

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L-FW322-07-NV100-DT Overview

Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA100, ROHS COMPLIANT, FSBGA-100

L-FW322-07-NV100-DT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Broadcom
package instruction	LFBGA, BGA100,12X12,32
Reach Compliance Code	compliant
Address bus width
boundary scan	NO
maximum clock frequency	24.5785 MHz
letter of agreement	ASYNC, BIT
Maximum data transfer rate	50 MBps
External data bus width
JESD-30 code	S-PBGA-B100
JESD-609 code	e1
length	10 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA100,12X12,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.46 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	10 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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FW322 07 NV129/NV100/T100

1394a PCI PHY/Link Open Host Controller Interface

Product Brief

Features

129-ball VTFSBGA/100-ball FSBGA/100-pin TQFP

lead-free package.

1394a-2000 OHCI link and PHY core function in a sin-

gle device:

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card designs.

— Compatibility with current

Microsoft Windows

driv-

ers and common applications.

— Interoperability with existing, as well as older, 1394

consumer electronics and peripherals products.

OHCI:

— Complies with the

1394 OHCI 1.1 Specification.

— OHCI 1.0 backwards compatible: configurable via

PCI bus commands to operate in either OHCI 1.0 or

OHCI 1.1 mode.

— Listed on

Windows

hardware compatibility list

http://testedproducts.windowsmarketplace.com.

— Compatible with

Microsoft Windows

and

MacOS

operating systems.

— 4 Kbyte isochronous transmit FIFO.

— 2 Kbyte asynchronous transmit FIFO.

— 4 Kbyte isochronous receive FIFO.

— 2 Kbyte asynchronous receive FIFO.

— Dedicated asynchronous and isochronous descrip-

tor-based DMA engines.

— Eight isochronous transmit/receive contexts.

— Prefetches isochronous transmit data.

— Supports posted write transactions.

— Supports parallel processing of incoming physical

read and write requests.

— May be used without an EEPROM when the system

BIOS is programmed with the EEPROM contents.

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000, Standard for a

High Performance Serial Bus.

— Two fully compliant cable ports, each supporting

400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic.

— Does not require external filter capacitor for PLL.

— Supports link-on as a part of the internal

PHY core-link interface.

— Supports arbitrated short bus reset to improve

utilization of the bus.

— Supports multispeed packet concatenation.

— Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V.

Product Brief

PCI:

— Revision 2.3 compliant.

— 33 MHz/32-bit operation.

— Programmable burst size thresholds for PCI data

transfer.

— Supports optimized memory read line, memory read

multiple, and memory write invalidate burst com-

mands.

— Supports

PCI Bus Power Management Interface

Specification

v.1.1.

— Supports CLKRUN# protocol per PCI Mobile Design

Guide.

— Supports

Mini PCI Specification

v1.0, including

Mini

PCI

power requirements.

— CardBus support per PC card standard release 8.0,

including 128 bytes of on-chip tuple memory.

Other Features

CMOS process.

3.3 V operation, 5 V tolerant inputs.

C serial ROM interface.

Note:

The T100 device does not support D3cold wakeup,

CLKRUN protocol,

Mini PCI

applications, or Card-

Bus applications.

www.agere.com

September 2006

L-FW322-07-NV100-DT Related Products

	L-FW322-07-NV100-DT	L-FW322-07-NV129-DT	L-FW322-07-NV129-DB	L-FW322-07-NV100-DB
Description	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA100, ROHS COMPLIANT, FSBGA-100	Micro Peripheral IC,	Micro Peripheral IC,	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PBGA100, ROHS COMPLIANT, FSBGA-100
Reach Compliance Code	compliant	compliant	compliant	compliant
Maker	Broadcom	Broadcom	Broadcom	-
Is Samacsys	-	N	N	N
Base Number Matches	-	1	1	1

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