The AS7C3513B is a high performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16
bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20 ns with output enable access times (t
OE
) of 5, 6, 7, 8 ns are ideal for
high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is high, the device enters standby mode. If inputs are still toggling, the device consumes I
SB
power. If the bus is static, then the full
standby power is reached (I
SB1
). The AS7C3513B is guaranteed not to exceed 18mW power consumption under nominal full standby
conditions.
A write cycle is accomplished by asserting write enable (WE), (UB) and/or (LB), and chip enable (CE). Data on the input pins I/O0 - I/O7,
and/or I/O8 – I/O15, is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices
should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), (UB) and (LB), and chip enable (CE), with write enable (WE) high. The chips
drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O0 – I/O7, and UB controls the higher bits, I/O8 – I/O15.
All chip inputs and outputs are TTL-compatible. The AS7C3513B is packaged in common industry standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–65
–55
–
Max
+5.0
V
CC
+0.50
1.0
+150
+125
20
Unit
V
V
W
o
C
o
C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
L
L
L
L
L
WE
X
H
H
H
L
L
L
H
X
OE
X
L
L
L
X
X
X
H
X
LB
X
L
H
L
L
L
H
X
H
UB
X
H
L
L
L
H
L
X
H
I/O0–I/O7
High Z
D
OUT
High Z
D
OUT
D
IN
D
IN
High Z
High Z
I/O8–I/O15
High Z
High Z
D
OUT
D
OUT
D
IN
High Z
D
IN
High Z
Mode
Standby (I
SB
, I
SBI
)
Read I/O0–I/O7 (I
CC
)
Read I/O8–I/O15 (I
CC
)
Read I/O0–I/O15 (I
CC
)
Write I/O0–I/O15 (I
CC
)
Write I/O0–I/O7 (I
CC
)
Write I/O8–I/O15 (I
CC
)
Output disable (I
CC
)
Key: X = Don’t care; L = Low; H = High
3/24/04, v.1.2
Alliance Semiconductor
P. 2 of 10
AS7C3513B
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature
V
IL
= -1.0V for pulse width less than 5ns
V
IH =
V
CC
+ 1.5V for pulse width less than 5ns
Symbol
V
CC
V
IH
V
IL
commercial
industrial
T
A
T
A
Min
3.0
2.0
–0.5
0
–40
Typical
3.3
–
–
–
–
Max
3.6
V
CC
+ 0.5
0.8
70
85
Unit
V
V
°C
°C
DC operating characteristics (over the operating range)
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