16 Megabit (512K x 32-Bit)
MCM SRAM
89C1632
16 Megabit (512k x 32-bit) SRAM MCM
CS 1-4
Address
OE, WE
Power
4Mb SRAM
4Mb SRAM
4Mb SRAM
4Mb SRAM
Ground
MCM
Memory
I/O 0-7
I/O 8-15
I/O 16-23
I/O 24-31
Logic Diagram
F
EATURES
:
• Four 512k x 8 SRAM architecture
• R
AD
-P
AK
® technology hardens against natural space radia-
tion technology
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
- SEL > 101MeV-cm
2
/mg
- SEU threshold = 3 MeV-cm
2
/mg
- SEU saturated cross section: 6E-9 cm
2
/bit
• Package: 68-pin quad flat package
• Fast access time: 20, 25 and 30 ns
• Completely static memory - no clock or timing strobe
required
• Internal bypass capacitor
• High-speed silicon-gate CMOS technology
• 5V or 3V ± 10% power supply
• Equal address and chip enable access times
• Three-state outputs
• All inputs and outputs are TTL compatible
D
ESCRIPTION
:
DDC’s 89C1632 high-performance 16 Megabit Multi-Chip
Module (MCM) Static Random Access Memory features a
greater than 100 krad (Si) total dose tolerance, depending
upon space mission. The four 4-Megabit SRAM die and
bypass capacitors are incorporated into a high-reliable her-
metic quad flat-pack ceramic package. With high-performance
silicon-gate CMOS technology, the 89C1632 reduces power
consumption and eliminates the need for external clocks or
timing strobes. It is equipped with output enable (OE) and four
byte enable (CS1 - CS4) inputs to allow greater system flexi-
bility. When OE input is high, the output is forced to high
impedance.
DDC’s patented R
AD
-P
AK
® packaging technology incorporates
radiation shielding in the microcircuit package. In a GEO orbit,
R
AD
-P
AK
provides true greater than 100 krad (Si) total radiation
dose tolerance, dependent upon space mission. It eliminates
the need for box shielding while providing the required radia-
tion shielding for a lifetime in orbit or a space mission. This
product is available with screening up to DDC’s self-defined
Class K.
01.10.05 Rev 3
All data sheets are subject to change without notice
1
(631) 567-5600 - www.ddc-web.com
©2016 Data Device Corporation.
All rights reserved.
16 Megabit (512K x 32-Bit) MCM SRAM
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
34-28, 42-36, 62-64, 7, 8
65
66
3-6
43-46, 48-56, 58-61, 9-12,
14-17, 19-22, 24-27
2, 67, 68
1, 18, 35, 52
13, 23, 47, 57
S
YMBOL
A0-A18
WE
OE
CS1 - CS4
I/O0-I/O31
NC
V
CC
V
SS
D
ESCRIPTION
Address Enable
WriteEnable
Output Enable
Chip Enable
Data Input/Output
No Connection
+5V Power Supply
Ground
89C1632
T
ABLE
2. 89C1632 A
BSOLUTE
M
AXIMUM
R
ATINGS
(V
OLTAGE REFERENCED TO
V
SS
= 0V)
P
ARAMETER
Power Supply Voltage Relative to V
SS
Voltage Relative to V
SS
for Any Pin Except V
CC
Power Dissipation
Operating Temperature
Storage Temperature
S
YMBOL
V
CC
V
IN
, V
OUT
P
D
T
A
T
S
M
IN
-0.5
-0.5
--
-55
-65
M
AX
+7.0
V
CC
+0.5
4.0
+125
+150
U
NITS
V
V
W
°
C
°
C
Memory
T
ABLE
3. 89C1632 R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Supply Voltage, (Operating Voltage Range)
Input High Voltage
Input Low Voltage
1. V
IH
(max) = V
CC
+ 2V ac (pulse width < 10ns) for I < 80 mA.
2. V
IL
(min) = -2.0V ac; (pulse width < 20 ns) for I < 80 mA.
S
YMBOL
V
CC
V
IH
V
IL
M
IN
4.5
2.2
-0.5
(2)
M
AX
5.5
V
CC
+ 0.5
(1)
0.8
U
NITS
V
V
V
T
ABLE
4. 89C1632 D
ELTA
L
IMITS
P
ARAMETER
I
CC
01.10.05 Rev 3
V
ARIATIONL
+10% of stated value in table 5
All data sheets are subject to change without notice
2
©2016 Data Device Corporation
All rights reserved.
16 Megabit (512K x 32-Bit) MCM SRAM
T
ABLE
4. 89C1632 D
ELTA
L
IMITS
P
ARAMETER
I
SB
I
SB1
I
LI
V
ARIATIONL
+10% of stated value in table 5
+10% of stated value in table 5
+10% of stated value in table 5
89C1632
T
ABLE
5. 89C1632 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Leakage Current
Output Leakage Current
Average Operating Current
Cycle Time:
20 ns
25 ns
30 ns
Standby Power Supply Current
CMOS Standby Power Supply
Current
Output Low Voltage
Output High Voltage
Input Capacitance
1
CS1 - CS4,
OE, WE
I/O0-7, I/O8-15, I/O16-23,
I/O24-31
Input / Output Capacitance
1
1. Guaranteed by design.
S
YMBOL
T
EST
C
ONDITIONS
I
LI
I
LO
I
CC
V
IN
= 0 to V
CC
CS = V
IH
, V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty, CS = V
IL
,
I
OUT
= 0 mA
V
IN
= V
IH
or V
IL
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
--
--
--
1, 2, 3
1, 2, 3
--
--
--
--
M
IN
-8.0
-8.0
T
YP
--
--
--
800
760
720
240
60
mA
mA
M
AX
+8.0
+8.0
U
NITS
uA
uA
mA
Memory
I
SB
I
SB1
CS= V
IH
, cycle time > 25ns
CS > V
CC
- 0.2V, f = 0 MHz, V
IN
>
V
CC
- 0.2V or
V
IN <
0.2V
I
OL
= + 8.0 mA
I
OH
= -4.0 mA
V
IN
= 0 V
V
OL
V
OH
C
IN
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
2.4
--
--
0.4
--
7
28
7
8
V
V
pF
C
OUT
V
I/O
= 0 V
4, 5, 6
pF
T
ABLE
6. 89C1632 AC O
PERATING
C
ONDITIONS AND
C
HARACTERISTICS
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Pulse Level
Output Timing Measurement Reference Level
Input Rise/Fall Time
01.10.05 Rev 3
M
IN
0.0
--
--
T
YP
--
--
--
M
AX
3.0
1.5
3.0
U
NITS
V
V
ns
All data sheets are subject to change without notice
3
©2016 Data Device Corporation
All rights reserved.
16 Megabit (512K x 32-Bit) MCM SRAM
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Timing Measurement Reference Level
M
IN
--
T
YP
--
89C1632
M
AX
1.5
U
NITS
V
T
ABLE
6. 89C1632 AC O
PERATING
C
ONDITIONS AND
C
HARACTERISTICS
T
ABLE
7. 89C1632 R
EAD
C
YCLE
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Read Cycle Time
-20
-25
-30
Address Access Time
-20
-25
-30
Chip Select to Output
-20
-25
-30
Output Enable to Output
-20
-25
-30
Output Enable to Low-Z Output
-20
-25
-30
Chip Enable to Low-Z Output
-20
-25
-30
Output Disable to High-Z Output
-20
-25
-30
Chip Disable to High-Z Output
-20
-25
-30
Output Hold from Address Change
-20
-25
-30
S
YMBOL
t
RC
S
UBGROUPS
9, 10, 11
20
25
30
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
3
3
3
--
--
--
--
--
--
5
6
8
--
--
--
ns
5
6
8
--
--
--
ns
3
3
3
--
--
--
ns
0
0
0
--
--
--
ns
--
--
--
10
12
14
ns
--
--
--
20
25
30
ns
--
--
--
20
25
30
ns
--
--
--
--
--
--
ns
M
IN
T
YP
M
AX
U
NITS
ns
t
AA
Memory
t
CO
t
OE
t
OLZ
t
LZ
t
OHZ
t
HZ
t
OH
01.10.05 Rev 3
All data sheets are subject to change without notice
4
©2016 Data Device Corporation
All rights reserved.
16 Megabit (512K x 32-Bit) MCM SRAM
T
ABLE
8. 89C1632 F
UNCTIONAL
D
ESCRIPTION
CS
H
L
L
L
1. X = don’t care.
WE
X
1
H
H
L
OE
X
1
H
L
X
1
M
ODE
Not Select
Output Disable
Read
Write
I/O P
IN
High-Z
High-Z
D
OUT
D
IN
89C1632
S
UPPLY
C
URRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
T
ABLE
9. 89C1632 W
RITE
C
YCLE
(V
CC
= 5.0 + 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Write Cycle Time
-20
-25
-30
Chip Select to End of Write
-20
-25
-30
Address Set-up Time
-20
-25
-30
Address Valid to End of Write
-20
-25
-30
Write Pulse Width (OE High)
-20
-25
-30
Write Pulse Width (OE Low)
-20
-25
-30
Write Recovery Time
-20
-25
-30
S
YMBOL
t
WC
S
UBGROUPS
9, 10, 11
20
25
30
9, 10, 11
14
17
20
9, 10, 11
0
0
0
9, 10, 11
14
17
20
9, 10, 11
14
17
20
9, 10, 11
20
25
30
9, 10, 11
0
0
0
--
--
--
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
M
IN
T
YP
M
AX
U
NITS
ns
Memory
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
01.10.05 Rev 3
All data sheets are subject to change without notice
5
©2016 Data Device Corporation
All rights reserved.
京公网安备 11010802033920号
EEWORLD
