X1M000201001011 datasheet, PDF

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X1M000201001011: DescriptionLVPECL Output Clock Oscillator,; CategoryPassive components oscillator; File Size475KB，7 Pages; ManufacturerSeiko Epson Corporation; Environmental Compliance

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X1M000201001011 Overview

LVPECL Output Clock Oscillator,

X1M000201001011 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Seiko Epson Corporation
Reach Compliance Code	unknown
Other features	STANDBY; ENABLE/DISABLE FUNCTION
maximum descent time	0.4 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
Installation features	SURFACE MOUNT
Number of terminals	6
Nominal operating frequency	106.25 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-5 °C
Oscillator type	LVPECL
Output load	50 OHM
physical size	5mm x 3.2mm x 1.4mm
longest rise time	0.4 ns
Maximum slew rate	60 mA
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %

X1M000201001011 Preview

Clock OSC

EG-2102CB

EG-2102CB 106.250000MHz +/-50ppm PGRN

Product name

X1M0002010010xx

Product Number / Ordering code

Please refer to the 9.Packing information about xx (last 2 digits)

Output waveform

LV-PECL

Pb free / Complies with EU RoHS directive

Reference weight Typ. 71 mg

1.Absolute maximum ratings

Parameter

Symbol

Maximum supply voltage

Storage temperature

Input voltage

Min.

-0.5

-55

-0.5

Typ.

-

Max.

4

125

Vcc+0.5

Unit

V

ºC

V

Conditions / Remarks

-

Storage as single product

ST or OE Terminal

Vcc-GND

T_stg

Vin

2.Specifications(characteristics)

Parameter

Symbol

Output frequency

Supply voltage

Operating temperature

Frequency tolerance

Current consumption

Stand-by current

Disable current

Symmetry

Output voltage(LV-PECL)

Output load condition(ECL)

Input voltage

Rise time

Fall time

Start-up time

Jitter

Min.

Typ.

Max.

Unit

MHz

V

ºC

x10

-6

mA

%

V

Ω

Conditions / Remarks

-

OE=Vcc,L_ECL=50ohm

-

OE=GND

As output crodding point

-

Terminated to Vcc-2.0V

OE Terminal

Phase jitter

Phase noise

f0

Vcc

T_use

f_tol

Icc

I_std

I_dis

SYM

V

OH

V

OL

L_ECL

V

IH

V

IL

t

r

tf

t_str

t

DJ

T

RJ

t

RMS

t

p-p

t

acc

t

PJ

L(f)

Frequency aging

f_age

-

106.2500

-

2.97

3.3

3.63

-5

-

85

-50

-

50

-

60

-

2.0

45

-

55

Vcc-1.025

2.35

Vcc-0.88

Vcc-1.81

1.6

Vcc-1.62

-

50

-

70% Vcc

-

30% Vcc

-

0.4

-

0.4

-

10

-

N/A

-

N/A

-

N/A

-

N/A

-

N/A

-

0.23

-

-52.9

-

-85.0

-

-116.1

-

-143.8

-

-151.9

-

-154.2

-

-10

-

10

ps

ms

ps

dBc/Hz

x10 /Year

-6

At 20% to 80% output swing

-

Deterministic Jitter

Random Jitter

δ(RMS of total distribution)

Peak to Peak

Accumulated Jitter(δ) n=2 to 50000 cycles

Off set Frequency: 12kHz to 20MHz

Off set 1Hz

Off set 10Hz

Off set 100Hz

Off set 1kHz

Off set 10kHz

Off set 100kHz

Off set 1MHz

@+25ºC first year

1 Page

3.Test circuit

1) To observe waveform and current (case 1)

Vcc

+3.3 V

________

A

By-pass

capacitor 2

Power

supply 2

Vcc

OUT

130 Ω

Test Point

OE

OE pin

NC

GND

82 Ω

By-pass

capacitor 1

Test Point

82 Ω

________

* The lines from OUT and OUT pin are same length.

* To measure the disable current, OE pin is connected to GND

2) To observe waveform and current (case 2)

A

+3.3 V

________

Test Point

OUT

50 Ω

Test Point

50 Ω

Vcc-2 V

By-pass

capacitor 2

Power

supply 2

Vcc

OE

OE pin

NC

GND

By-pass

capacitor 1

________

* The lines from OUT and OUT pin are same length.

* To measure the disable current, OE pin is connected to GND

3) Measurement condition

A) Oscilloscope

•Bandwidth should be 5 times higher than DUT’s output frequency (4 GHz).

•Probe ground should be placed closely from test point and lead length should be as short as possible.

B) By-pass capacitor 1 (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.

C) By-pass capacitor 2 (approx. 10 μF) places closely between power supply terminals on the board.

D) Use the current meter whose internal impedance value is small.

E) Power supply

• Start up time (0 Vg90 %Vcc) of power source should be more than 150 μs and

slew rate should be less than 19.8 mV/μs.

• Impedance of power supply should be as low as possible.

2 Page

4.Timing chart

Vcc

80 % of amplitude

tr

tf

________

OUT

20 % of amplitude

Vcc-2 V

OUT

GND

tw

SYM = tw / t

t

5.External dimensions

(Unit: mm)

0.64

6.Footprint(Recommended)

0.84

(Unit: mm)

#6

#5 #4

3.2±0.2

1P 1X1A

#1

#2 #3

#3

1.4±0.15

#2

1.27

#1

1.27

2.54

5.0±0.2

2.54

To maintain stable operation, provide a 0.01uF to 0.1uF

by-pass capacitor at a location as near as possible to the

power source terminal of the crystal product (between Vcc

- GND).

7.Reflow profile

Reflow condition (Follow of JEDEC STD-020D.01)

Temperature[C]

300

250

200

150

100

50

Time

+25CtoPeak

0

60

120 180 240 300 360 420 480 540 600 660 720 780

Time[s]

;+217C

Tsmax;+200C



TL

TP



;+260C

+255C

Avg.

Ramp-up

3



C/sMax.

0.6



tp

;20sto40s

tL

60sto150s

(+217Cover)

Tsmin;+150C

ts

60sto180s

(+150Cto+200C)

3 Page

2.0

E

212.50P

1.3

Ramp-down

6C/sMax.

1.6

#4

#5

#6

8.PCB layout (2 layers, 2nd layer is all GND pattern)

Case 1

Terminators place near the input device.

Thevenin parallel

termination

Line width (B) is estimated as follows

εr : Relative dielectric constant of the board

H : Board thickness between line and GND

C : Line thickness

Two output lines are same length and width

By-pass capacitor (approx. 10 μF) places closely

between power supply terminals on the board

By-pass capacitor (approx. 0.01 μF to 0.1 μF)

places closely between Vcc and GND

Connected to 2nd layer GND through via-hole

* By-pass capacitor (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.

* By-pass capacitor (approx. 10 μF) places closely between power supply terminals on the board.

* Please design the two output lines by characteristic impedance 50 Ω and

same length, and try to make the output lines as short as possible.

* Terminators place near the input device.

4 Page

Case 2

Terminators place near the input device.

Parallel termination

Line width (B) is estimated as follows

εr : Relative dielectric constant of the board

H : Board thickness between line and GND

C : Line thickness

Two output lines are same length and width

By-pass capacitor (approx. 10 μF) places closely

between power supply terminals on the board

By-pass capacitor (approx. 0.01 μF to 0.1 μF)

places closely between Vcc and GND

Connected to 2nd layer GND through via-hole

* By-pass capacitor (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.

* By-pass capacitor (approx. 10 μF) places closely between power supply terminals on the board.

* Please design the two output lines by characteristic impedance 50 Ω and

same length, and try to make the output lines as short as possible.

* Terminators place near the input device.

9.Packing information

[ 1 ]Product number last 2 digits code(xx) description

The recommended code is "00"

Code

13

00

Condition

500pcs / Reel

1000pcs / Reel

X1M0002010010xx

Code

01

11

12

Condition

Any Q'ty vinyl bag(Tape cut)

Any Q'ty / Reel

250pcs / Reel

5 Page

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X1M000201001011 Related Products

	X1M000201001011	X1M000201001000	X1M000201001001	X1M000201001012	X1M000201001013
Description	LVPECL Output Clock Oscillator,	LVPECL Output Clock Oscillator,	LVPECL Output Clock Oscillator,	LVPECL Output Clock Oscillator,	LVPECL Output Clock Oscillator,
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	Seiko Epson Corporation	Seiko Epson Corporation	Seiko Epson Corporation	Seiko Epson Corporation	Seiko Epson Corporation
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
Other features	STANDBY; ENABLE/DISABLE FUNCTION	STANDBY; ENABLE/DISABLE FUNCTION	STANDBY; ENABLE/DISABLE FUNCTION	STANDBY; ENABLE/DISABLE FUNCTION	STANDBY; ENABLE/DISABLE FUNCTION
maximum descent time	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns
Frequency Adjustment - Mechanical	NO	NO	NO	NO	NO
frequency stability	50%	50%	50%	50%	50%
Installation features	SURFACE MOUNT	SURFACE MOUNT	SURFACE MOUNT	SURFACE MOUNT	SURFACE MOUNT
Number of terminals	6	6	6	6	6
Nominal operating frequency	106.25 MHz	106.25 MHz	106.25 MHz	106.25 MHz	106.25 MHz
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-5 °C	-5 °C	-5 °C	-5 °C	-5 °C
Oscillator type	LVPECL	LVPECL	LVPECL	LVPECL	LVPECL
Output load	50 OHM	50 OHM	50 OHM	50 OHM	50 OHM
physical size	5mm x 3.2mm x 1.4mm	5mm x 3.2mm x 1.4mm	5mm x 3.2mm x 1.4mm	5mm x 3.2mm x 1.4mm	5mm x 3.2mm x 1.4mm
longest rise time	0.4 ns	0.4 ns	0.4 ns	0.4 ns	0.4 ns
Maximum slew rate	60 mA	60 mA	60 mA	60 mA	60 mA
Maximum supply voltage	3.63 V	3.63 V	3.63 V	3.63 V	3.63 V
Minimum supply voltage	2.97 V	2.97 V	2.97 V	2.97 V	2.97 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
maximum symmetry	55/45 %	55/45 %	55/45 %	55/45 %	55/45 %

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