i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
16Mx72 DDR SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR SDRAM Data Rate = 200, 250, 266, 333Mbps
Package:
•
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture
(one per byte)
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Industrial, Enhanced and Military Temperature
Ranges
Organized as 16M x 72/80
Weight: AS4DDR16M72PBG = 3.50 grams typical
* This product and or it’s specifications is subject to change without notice..
BENEFITS
40% SPACE SAVINGS
Reduced part count
Reduced I/O count
•
34% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 72 density
(AS4DDR32M72PBG)
Meets or exceeds published specifications of
White’s W3E16M72S-XBX
Monolithic Solution
O
P
T
I
O
N
S
11.9
11.9
11.9
11.9
11.9
Integrated MCP Solution
S
A
V
I
N
G
S
22.3
25
32
Area
I/O
Count
5 x 265mm2 = 1328mm2 Plus
5 x 66 pins = 320 pins
800mm2
219 Balls
40+%
34 %
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
SDRAM-DDR PINOUT TOP VIEW
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VCCQ
VCCQ
DQ16
DQ17
DQ31
VSS
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VCC
VCC
DQ18
DQ19
DQ29
DQ30
DQ3
DQ4
DQ10
DQ11
VCC
VCC
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
DQ6
DQ5
DQ8
DQ9
VCCQ
VSSQ
A12
DNU
DNU
DNU
VSS
VSS
DQ22
DQ23
DQ26
DQ25
DQ7
DQML0
VCC
DQMH0 DQSH3 DQSL0 DQSH0
BA0
BA1
DQSL1 DQSH1
VREF
DQML1
VSS
NC
DQ24
CA S0\
WE0\
VCC
CLK0
DQSL3
RAS1\
WE1\
VSS
DQMH1
CLK1
CS0\
RAS0\
VCC
CKE0
CLKO\
CAS\
CS1\
VSS
CLK1\
CKE1
VSS
VSS
VCC
VCCQ
VSS
VCC
VSS
VSS
VCCQ
VCC
VSS
VSS
VCC
VCCQ
VSS
VCC
VSS
VSS
VCCQ
VCC
CLK3\
CKE3
VCC
CS3\
DQSL4
CLK2\
CKE2
VSS
RAS2\
CS2\
NC
CLK3
VCC
CAS3\
RAS3\
DQSL2
CLK2
VSS
WE2\
CAS2\
DQ56 DQMH3
VCC
WE3\
DQML3
CKE4 DQMH4
CLK4
CAS4\
WE4\
RAS4\
CS4\
DQMH2
VSS
DQML2
DQ39
DQ57
DQ58
DQ55
DQ54
DQSH4 CLK4\
DQ73
DQ72
DQ71
DQ70
DQML4 DQSH2\ DQ41
DQ40
DQ37
DQ38
DQ60
DQ59
DQ53
DQ52
VSS
VSS
DQ75
DQ74
DQ69
DQ68
VCC
VCC
DQ43
DQ42
DQ36
DQ35
DQ62
DQ61
DQ51
DQ50
VCC
VCC
DQ77
DQ76
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
VSS
DQ63
DQ49
DQ48
VCCQ
VCCQ
DQ79
DQ78
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VCC
Ground
Array Power
D/Q Power
Address
Data IO
CNTRL
Address/DNU
UNPOPULATED
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
FUNCTIONAL BLOCK DIAGRAM
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
PIN DEFINITIONS / FUNCTIONAL DESCRIPTION
BGA Locations
SYMBOL
F4, F16, G5, G15, K1, K12,
CKx, CKx\
L2, L13, N6, M8
DESCRIPTION
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CKx and negative edge of CKx\.
Output data (DQ's and DQS) is referenced to the crossings of the differential clock
inputs.
Clock Enable: CKE controls the clock inputs. CKE high enables, CKE Low disables
the clock input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE
is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE
is Asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input buffers are disabled
during POWER-DOWN Input buffers are disabled during SELF REFRESH. CKE is an
SSTL-2 input but will detect an LVCMOS LOW level after VCC is applied
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) contained
words. All commands are masked with CSx\ is registered HIGH. CSx\ provides for
external bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
Command Inputs: RASx, CASx and Wex\ define the command being entered.
G4, G16, K2, K13, M6
CKEx
G1, G13, K4, K16, M12
CSx\
F4, F16, G5, G15, K1, K12, RASx\, CASx\,
L2, L13, N7, M9
Wex\
G4, G16, K2, K14, M7
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DQMLx, DQMHx
DQMLx or Hx is sampled HIGH at time of a WRITE access. DM is sampled on both
edges of DQSLx and DQSHx.
BA0, BA1
Bank Address Inputs: BA0, BA1, define which bank an ACTIVE READ, WRITE or
PRECHARGE Command is being applied.
Address Input: Provide the row address for Active commands, and the column address
and auto precharge bit (A10) for READ / WRITE commands to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank or all banks.
The address inputs also provide the op-code during a MODE RESISTER SET
command.
E8, E9
A7, A8, A9, A10, B7, B8,
B9, B10, C7, C8. C9, C10, A0-11, A12
D7
A2, A3, A4, A13, A14, B1,
B2, B3, B4, B13, B14, B15,
B16, C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2, D3,
D4, D13, D14, D15, D16,
E1, E16, M1, M16, N1, N2, DQ0-79
N3, N4, N13, N14, N15,
N16, T2, T3, T4, T13, T14,
T15, N7, N8, N9, N10, P7,
P8, P9, P10, R7, R8, R9,
R10, T7, T8, T9, T10
E6, E7, E10, E11, F5, K5,
DQSLX, DQSHX
L12, N5, N12, E5
B11, B12, C5, C6, E3, F3,
G3, H3, H12, H16, J3, J12,
VCC
J16, K3, L3, M3, P11, P12,
R5, R6, T16
A11, A12, D5, D6, H4, H15,
VCCQ
J4, J15, T5, T6
A5, A6, A16, B5, B6, C11,
C12, D11, D12, E14, F14,
G14, H1, H2, H5, H13,
VSS
H14, J1, J2, J5, J13, J14,
K14, L14, P5, P6, R11.
R12, T1, T11, T12, M14
E12
AS4DDR16M72PBG
Rev. 2.1 06/09
Data I/O
Data Stobe: Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data. It is used to capture data
Core Power Supply
I/O Power Supply
Ground (Digital)
VREF
SSTL-2 Reference Voltage
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
i PEM
1.2 Gb SDRAM-DDR
Gb
Austin Semiconductor, Inc.
AS4DDR16M72PBG
GENERAL DESCRIPTION
The 1.2Gb DDR SDRAM MCM, is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128MB(1.2Gb) DDR SDRAM MCM uses a DDR
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 128MB DDR SDRAM effectively consists of a single 2n-
bit wide, one-clock-cycle data tansfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
and by the memory contoller during WRITEs. DQS is
edgealigned with data for READs and center-aligned with
data for WRITEs. Each chip has two data strobes, one for
the lower byte and one for the upper byte.
The 128MB DDR SDRAM operates from a differential clock
(CLK and CLK#); the crossing of CLK going HIGH and CLK#
going LOW will be referred to as the positive edge of CLK.
Commands (address and control signals) are registered
at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE
command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and
the starting column location for the burst access.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-12 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The
following sections provide detailed information covering device
initialization, register defi nition, command descriptions and
device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first
be applied to V
CC
and V
CCQ
simultaneously, and then to V
REF
(and to the system V
TT
). V
TT
must be applied after V
CCQ
to avoid
device latch-up, which may cause permanent damage to the
device. V
REF
can be applied any time after V
CCQ
but is expected
to be nominally coincident with V
TT
. Except for CKE, inputs are
not recognized as valid until after V
REF
is applied. CKE is an
SSTL_2 input but will detect an LVCMOS LOW level after V
CC
is
applied. Maintaining an LVCMOS LOW level on CKE during
powerup is required to ensure that the DQ and DQS outputs
will be in the High-Z state, where they will remain until driven in
normal operation (by a read access). After all power supply and
reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200µs delay prior to applying an executable
command.
Once the 200µs delay has been satisfied, a DESELECT or
NOP command should be applied, and CKE should be brought
HIGH. Following the NOP command, a PRECHARGE ALL
command should be applied. Next a LOAD MODE REGISTER
command should be issued for the extended mode register
(BA1 LOW and BA0 HIGH) to enable the DLL, followed by another
LOAD MODE REGISTER command to the mode register (BA0/
BA1 both LOW) to reset the DLL and to program the operating
The DDR SDRAM provides for programmable READ or parameters. Two-hundred clock cycles are required between
WRITE burst lengths of 2, 4, or 8 locations. An auto precharge the DLL reset and any READ command. A PRECHARGE ALL
function may be enabled to provide a selftimed row command should then be applied, placing the device in the all
precharge that is initiated at the end of the burst access.
banks idle state.
The pipelined, multibank architecture of DDR SDRAMs allows Once in the idle state, two AUTO REFRESH cycles must be
for concurrent operation, thereby providing high effective performed (t
RFC
must be satisfi ed.) Additionally, a LOAD MODE
bandwidth by hiding row precharge and activation time.
REGISTER command for the mode register with the reset DLL
bit deactivated (i.e., to program operating parameters without
An auto refresh mode is provided, along with a powersaving resetting
the
DLL)
is
required.
Following
power-down mode.
these requirements, the DDR SDRAM is ready for normal
operation.
AS4DDR16M72PBG
Rev. 2.1 06/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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