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AS4SD2M32DGX-75ET

Description
512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM
File Size2MB,52 Pages
ManufacturerAUSTIN
Websitehttp://www.austinsemiconductor.com/
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AS4SD2M32DGX-75ET Overview

512K x 32 x 4 Banks (64-Mb) Synchronous SDRAM

SDRAM
Austin Semiconductor, Inc.
512K x 32 x 4 Banks (64-Mb)
Synchronous SDRAM
FEATURES
• Full Military temp (-55°C to 125°C) processing available
• Configuration: 512K x 32 x 4 banks
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT & ET)
• 64ms, 4,096 cycle refresh (IT & ET)
• <16ms 4,096 cycle refresh (XT)
• WRITE Recovery (t
WR
= “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
AS4SD2M32
PIN ASSIGNMENT
(Top View)
86-Pin TSOPII
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
OPTIONS
• Plastic TSOPII-EX
MARKING
DGX
-6
-7
-7.5
IT
ET
XT***
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
Timing (Cycle Time)
6.0ns CL=3
7.0ns CL=3
7.5ns CL=3
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C)
-Enhanced Temp
(-45°C to +105°C)
-Extended Temp (-55°C to 125°C)
2M x 32
Configuration
512K x 32 x 4
Refresh Count
4K
Row Addressing
4K (A0-A10)
Bank Addressing
4 (BA0, BA1)
Column Addressing
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
GRADE FREQUENCY CL = 2** CL = 3**
**CL = CAS (READ) latency
***Consult Factory
SETUP
TIME
1.5ns
HOLD
TIME
0.8ns
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4SD2M32
Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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