SDRAM
Austin Semiconductor, Inc.
512K x 32 x 4 Banks (64-Mb)
Synchronous SDRAM
FEATURES
• Full Military temp (-55°C to 125°C) processing available
• Configuration: 512K x 32 x 4 banks
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode (IT & ET)
• 64ms, 4,096 cycle refresh (IT & ET)
• <16ms 4,096 cycle refresh (XT)
• WRITE Recovery (t
WR
= “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
AS4SD2M32
PIN ASSIGNMENT
(Top View)
86-Pin TSOPII
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
OPTIONS
• Plastic TSOPII-EX
•
MARKING
DGX
-6
-7
-7.5
IT
ET
XT***
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
Timing (Cycle Time)
6.0ns CL=3
7.0ns CL=3
7.5ns CL=3
Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C)
-Enhanced Temp
(-45°C to +105°C)
-Extended Temp (-55°C to 125°C)
•
2M x 32
Configuration
512K x 32 x 4
Refresh Count
4K
Row Addressing
4K (A0-A10)
Bank Addressing
4 (BA0, BA1)
Column Addressing
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
GRADE FREQUENCY CL = 2** CL = 3**
**CL = CAS (READ) latency
***Consult Factory
SETUP
TIME
1.5ns
HOLD
TIME
0.8ns
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4SD2M32
Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SDRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic ran-
dom-access memory containing 67,108,864 bits. It is internally
configured as a quad-bank DRAM with a synchronous inter-
face (all signals are registered on the positive edge of the clock
signal, CLK). Each of the 16,777,216-bit banks is organized as
2,048 rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A10 select the row). The address bits reg-
istered coincident with the READ or WRITE command are used
to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4, or 8 locations, or the full page, with a
burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at
the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random operation. Precharging one
bank while accessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed, random-
access operation.
The 64Mb SDRAM is designed to operate in 3.3V memory
systems. An auto refresh mode is provided, along with a power-
saving, power-down mode. All inputs and outputs are LVTTL-
compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks to hide precharge
time and the capability to randomly change column addresses
on each clock cycle during a burst access.
AS4SD2M32
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
DQM0-3
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
32
32
MODE
REGISTER
11
REFRESH
CONTROLLER
DQ 0-31
SELF
REFRESH
CONTROLLER
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
11
DATA OUT
BUFFER
32
32
V
DD
/V
DDQ
GND/GNDQ
REFRESH
COUNTER
2048
2048
2048
2048
ROW
DECODER
MULTIPLEXER
MEMORY
CELL
ARRAY
11
ROW
ADDRESS
LATCH
11
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP
I/O GATE
COLUMN
ADDRESS
LATCH
256
(x
32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS
BUFFER
AS4SD2M32
Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SDRAM
Austin Semiconductor, Inc.
PIN DESCRIPTIONS
PIN NUMBER
68
SYMBOL
CLK
TYPE
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CLK. CLK also
Input
increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SLEF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank) or CLOCK
SUSPEND operation (burst/access in progress). CKE is
Input
synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after
exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Chip Select: CS\ enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS\ is registered HIGH. CS\ provides for external
bank selection on systems with multiple banks. CS\ in considered
part of the command code.
Command Inputs: WE\, CAS\ and RAS\ (along with CS\) define
the command being entered.
Input/Output Mask: DQM is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DWM is sampled HIGH during a WRITE
cycle. The outptu buffers are placed in a High-Z state (two-clock
latency) when DQM is sampled HIGH during a READ cycle.
DQM0 corresponds to DQ0-7, DQM2 to DQ16-23, DQM3 to
DQ24-31
Bank Address Inputs: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
AS4SD2M32
67
CKE
20
CS\
Input
17, 18, 19
WE\, CAS\,
RAS\
Input
16,71,28,59
DQM0, DQM1,
DQM2, DQM3
Input
22, 23
BA0, BA1
Input
25, 26, 27, 60, 61, 62, 63, 64,
65, 66, 24
A0 - A10
Address Inputs: A0-A12 are sampled during the ACTIVE
command (row address A0-A12) and READ/WRITE command
(column-address A0-A8; with A10 defining auto precharge) to
select one location out of the memory array in the respective
Input
bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be prechaged (A10 [HIGH]) or bank
selected by (A10 [LOW]). The address inputs also provide the
op-code during LOAD MODE REGISTER COMMAND.
2,4,5,7,8,10,11,13,74,76,77,
79,80,82,83,85,31,33,34,36,3
7,39,40,42,45,47,48,50,51,53
,54,56
14, 21, 30, 57, 69, 70, 73
3,9,35,41,49,55,75,81
6,12,32,38,46,52,78,84
1,15,29,43
44,58,72,86
AS4SD2M32
Rev. 1.0 1/08
DQ0 - DQ31
I/O
Data Input/Output: Data bus
NC
V
DD
Q
V
SS
Q
V
DD
V
SS
No Connect: These pins should be left unconnected.
DQ Power: Isolated DQ power to the die for improved noise
Supply
immunity.
DQ Ground: Isolated DQ ground to the die for imporved noise
Supply
immunity.
Supply Power Supply: +3.3V ±0.3V
Supply Ground
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
---
3
SDRAM
Austin Semiconductor, Inc.
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAMs are quad-bank DRAMs
that operate at 3.3V and include a synchronous interface (all
signals are registered on the positive edge of the clock signal,
CLK). Each of the 16,777,216-bit banks is organized as 2,048
rows by 256 columns by 32 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0 - A10 select the row). The address bits
(A0 - A7) registered coincident with the READ or WRITE
command are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information covering
device initialization, register definition, command descriptions
and device operation.
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure 1.
The mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4 - M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the write burst mode, and M10, M11 and
M12 are reserved for future use.
The mode register must be loaded when all banks are idle,
and the controller must wait the specified time before initiating
the subsequent operation. Violating either of these require-
ments will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Figure
1. The burst length determines the maximum number of column
locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types, and a
full-page burst is available for the sequential types. The full-
page burst is used in conjunction with the BURST TERMI-
NATE command to generate arbitrary burst lengths.
Reserved states should not be used as unknown opera-
tion or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is reached.
The clock is uniquely selected by A1-A8 when the burst length
is set to two; by A2-A7 when the burst length is set to four, and
by A3-A7 when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the start-
ing location within the block. Full-page bursts wrap within the
page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column ad-
dress, shown in table 1.
AS4SD2M32
Initialization
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied to
VDD and VDDQ (simultaneously) and the clock is stable (stable
clock is defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a 100μs delay
prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100μs
period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
Once the 100μs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
then be precharged, thereby placing the device in the all banks
idle state.
Once in the idle state, two AUTO REFRESH cycles must
be preformed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for mode register programming. Because
the mode register will power up in an unknown state, it should
be loaded prior to applying any operational command.
Register Definition
MODE REGISTER
The mode register is used to define the specific mode of
operation of the SDRAM. This definition includes the
AS4SD2M32
Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SDRAM
Austin Semiconductor, Inc.
AS4SD2M32
FIGURE 1: Mode Register Definition TABLE 1: Burst Definition
BURST
LENGTH
BA1
BA0
2
4
8
Full
Page
(y)
STARTING
ORDER OF ACCESSES WITHIN A BURST
COLUMN TYPE = SEQUENTIAL TYPE = INTERLEAVED
A0
0
0-1
0-1
1
1-0
1-0
A1 A0
0 0
0-1-2-3
0-1-2-3
0 1
1-2-3-0
1-0-3-2
1 0
2-3-0-1
2-3-0-1
1 1
3-0-1-2
3-2-1-0
A2 A1 A0
0 0 0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0 0 1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0 1 0
2-3-4-5-6-7-0-1-
2-3-0-1-6-7-4-5
0 1 1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1 0 0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1 0 1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1 1 0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1 1 1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Cn, Cn+1, Cn+2, Cn+3,
n=A0-A7
Cn+4…
Not Supported
(location 0-y)
…Cn-1,
Cn…
NOTES:
1. For full-page access: y=512
2. For a burst length of two, A1-A7 select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A7 select the block-of-four burst;
A0-A1 selects the starting column within the block.
4. For a burst length of eight, A3-A7 select the block-of-eight burst;
A0-A2 selects the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A7 select the
starting column.
6. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
7. For a burst length of one, A0-A7 select the unique column to be
accessed, and mode register bit M3 is ignored.
AS4SD2M32
Rev. 1.0 1/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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