ABRIDGED DATA SHEET
Rev 1; 4/09
1Kb I
2
C/SMBus EEPROM with SHA-1 Engine
General Description
The DS28CN01 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the Federal Information Publications (FIPS)
180-1/180-2 and ISO/IEC 10118-3 Secure Hash
Algorithm (SHA-1). The memory is organized as four
32-byte pages. Data copy protection and EPROM emu-
lation features are supported for each memory page.
Each DS28CN01 has a guaranteed unique factory-pro-
grammed 64-bit registration number. Communication with
the DS28CN01 is accomplished through an industry-
standard I
2
C-compatible and SMBus™-compatible
interface. The SMBus timeout feature resets the
device’s interface if a bus-timeout fault condition is
detected.
Features
♦
1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
♦
Dedicated Hardware-Accelerated SHA-1 Engine
for Generating SHA-1 MACs
♦
EEPROM Memory Pages Can Be Individually
Copy Protected or Put Into EPROM Mode
(Program from 1 to 0 Only)
♦
Write Access Requires Knowledge of the Secret
and the Capability of Computing and Transmitting
a 160-Bit MAC as Authorization
♦
Unique, Factory-Programmed, and Tested 64-Bit
Registration Number Assures Absolute
Traceability Because No Two Parts are Alike
♦
Endurance 200,000 Cycles at +25°C
♦
Serial Interface User Programmable for I
2
C Bus
and SMBus Compatibility
♦
Supports 100kHz and 400kHz I
2
C Communication
Speeds
♦
+5.5V Tolerant Interface Pins
♦
Operating Ranges: +1.62V to +5.5V, -40°C to +85°C
♦
8-Pin µSOP Package
DS28CN01
Applications
PCB Unique Serialization
Accessory and Peripheral Identification
Equipment Registration and License
Management
Network Node Identification
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
Pin Configuration
PART
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 μSOP
8 μSOP
DS28CN01U-A00+
TOP VIEW
AD0
AD1
N.C.
GND
1
2
3
4
+
DS28CN01
8
7
6
5
V
CC
N.C.
SCL
SDA
DS28CN01U-A00+T
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
μ
SOP
Typical Operating Circuit appears at end of data sheet.
SMBus is a trademark of Intel Corp.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
ABRIDGED DATA SHEET
1Kb I
2
C/SMBus EEPROM with SHA-1 Engine
DS28CN01
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.........-0.5V to +6V
Maximum Current on Any Pin ...........................................±20mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Supply Voltage
Standby Current
Operating Current
Power-Up Wait Time
EEPROM
Programming Time
Programming Current
Endurance (Notes 3, 4, 5)
Data Retention (Notes 6, 7, 8)
SHA-1 ENGINE
SHA-1 Computation Time
SHA-1 Computation Current
t
CSHA
I
LCSHA
See full version of the data sheet.
See full version of the data sheet.
0.3 ×
V
CC
0.25 ×
V
CC
V
CCMAX
+ 0.3V
V
CCMAX
+ 0.3V
ms
mA
t
PROG
I
PROG
N
CY
t
DR
V
CC
2.0V
10
45
1.2
200,000
50,000
40
V
CC
< 2.0V
V
CC
= +5.5V
At +25°C
At +85°C
At +85°C
ms
mA
—
Years
SYMBOL
V
CC
I
CCS
I
CCA
t
POIP
Bus idle, V
CC
= +5.5V
Bus active at 400kHz, V
CC
= +5.5V
(Note 2)
CONDITIONS
MIN
1.62
TYP
MAX
5.50
5.5
500
5
UNITS
V
μA
μA
μs
SCL, SDA, AD1, AD0 PINS (Notes 9, 10)
V
CC
Low-Level Input Voltage
V
IL
V
CC
< 2.0V
V
CC
High-Level Input Voltage
V
IH
V
CC
< 2.0V
V
CC
V
HYS
V
CC
< 2.0V
Low-Level Output Voltage at
4mA Sink Current, Open Drain
V
CC
V
OL
2.0V
2.0V
2.0V
-0.3
0.7 ×
V
CC
0.8 ×
V
CC
0.05 ×
V
CC
0.1 ×
V
CC
0.4
0.2 ×
V
CC
V
2.0V
-0.3
V
V
Hysteresis of Schmitt Trigger
Inputs (Note 2)
V
V
CC
< 2.0V
2
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ABRIDGED DATA SHEET
1Kb I
2
C/SMBus EEPROM with SHA-1 Engine
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Output Fall Time from V
IH(MIN)
to
V
IL(MAX)
with a Bus Capacitance
from 10pF to 400pF (Notes 2, 11)
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current with an Input
Voltage Between 0.1V
CC
and
0.9V
CCMAX
Input Capacitance
SCL Clock Frequency
Bus Timeout
Hold-Time (Repeated) START
Condition; After this Period, the
First Clock Pulse is Generated
Low Period of the SCL Clock
(Note 14)
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time (Notes 15, 16)
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus
Line
SYMBOL
V
CC
t
OF
V
CC
< 2.0V
t
SP
(Note 2)
2.0V
CONDITIONS
MIN
20 +
0.1C
B
20 +
0.1C
B
TYP
MAX
250
ns
300
50
ns
UNITS
DS28CN01
I
I
C
I
f
SCL
t
TIMEOUT
t
HD:STA
(Note 12)
(Note 2)
(Note 13)
(Note 13)
(Note 14)
V
CC
2.7V
2.0V
-10
+10
10
400
μA
pF
kHz
ms
μs
25
0.6
1.3
1.5
1.9
0.6
0.6
0.3
0.3
0.3
100
0.6
1.3
75
t
LOW
t
HIGH
t
SU:STA
V
CC
μs
μs
μs
0.9
1.1
1.5
ns
μs
μs
400
pF
μs
V
CC
< 2.0V
(Note 14)
(Note 14)
V
CC
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
V
CC
2.7V
2.0V
V
CC
< 2.0V
(Notes 2, 14, 17)
(Note 14)
(Note 14)
(Notes 2, 14)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Guaranteed by design, characterization, and/or simulation only and not production tested.
This specification is valid for each 8-byte memory row.
Write-cycle endurance is degraded as T
A
increases.
Not 100% production tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T
A
increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
Note 8:
EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-time storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
Note 9:
All values are referred to V
IH(MIN)
and V
IL(MAX)
levels.
Note 10:
See Figure 3.
Note 11:
C
B
= Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I
2
C
Bus Specification v2.1 are allowed.
_______________________________________________________________________________________
3
ABRIDGED DATA SHEET
1Kb I
2
C/SMBus EEPROM with SHA-1 Engine
DS28CN01
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40°C to +85°C.) (Note 1)
Note 12:
The DS28CN01 does not obstruct the SDA and SCL lines if V
cc
is switched off.
Note 13:
The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1
and
SCL stays at the same logic
level or SDA stays low for this interval, the DS28CN01 behaves as though it has sensed a STOP condition.
Note 14:
System requirement.
Note 15:
The DS28CN01 provides a hold time of at least 300ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 16:
The master can provide a hold time of 0ns minimum when writing to the device. This 0ns minimum is guaranteed by
design, characterization, and/or simulation only, and not production tested.
Note 17:
A fast-mode I
2
C bus device can be used in a standard-mode I
2
C bus system, but the requirement t
SU:DAT
≥
250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250
= 1250ns (according to the standard-mode I
2
C bus specification) before the SCL line is released.
Pin Description
PIN
1
2
3, 7
4
5
6
8
NAME
AD0
AD1
N.C.
GND
SDA
SCL
V
CC
FUNCTION
Device Address Input Pin to Select the Slave Address. Sets slave address bits A[1:0] and must be
connected to either GND, SDA, SCL, or V
CC
.
Device Address Input Pin to Select the Slave Address. Sets slave address bits A[3:2] and must be
connected to either GND, SDA, SCL, or V
CC
.
No Connection
Ground Supply
I
2
C/SMBus Bidirectional Serial Data Line. This pin must be connected to V
CC
through a pullup resistor.
I
2
C/SMBus Serial Clock Input. This pin must be connected to V
CC
through a pullup resistor.
Power-Supply Input
Detailed Description
The DS28CN01 features a serial I
2
C/SMBus interface,
1Kb of SHA-1 secure EEPROM, a register page, and a
unique registration number, as shown in the
Block
Diagram.
The device communicates with a host proces-
sor through its I
2
C interface in standard mode or in fast
mode. The user can switch the interface from I
2
C bus
mode to SMBus mode. Two 4-level address pins allow
16 DS28CN01s to reside on the same bus segment.
Serial Communication Interface
The serial interface uses a data line (SDA) plus a clock
signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply volt-
age through a pullup resistor. When there is no commu-
nication, both lines are high. The output stages of
devices connected to the bus must have an open-drain
or open-collector output to perform the wired-AND
function. Data can be transferred at rates of up to
100kbps in the standard mode, and up to 400kbps in
the fast mode. The DS28CN01 works in both modes.
A device that sends data on the bus is defined as a
transmitter and a device receiving data is a receiver.
The device that controls the communication is called a
master. The devices that are controlled by the master
are slaves. The DS28CN01 is a slave device.
Device Operation
Read and write access to the DS28CN01 is controlled
through the I
2
C/SMBus serial interface. Since the
DS28CN01 has memory areas and registers of different
characteristics, there are several special cases to con-
sider. See the
Read and Write
section in the full data
sheet for details.
4
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ABRIDGED DATA SHEET
1Kb I
2
C/SMBus EEPROM with SHA-1 Engine
Block Diagram
V
CC
AD_
SCL
SDA
I
2
C/SMBUS
FUNCTION
CONTROL
MEMORY AND
SHA-1 ENGINE
CONTROL
DS28CN01
MAC OUTPUT
BUFFER
64-BIT UNIQUE
NUMBER
MAC
COMPARATOR
SHA-1
ENGINE
8-BYTE WRITE
BUFFER
SECRET
MEMORY
REGISTER
PAGE
DS28CN01
USER EEPROM
4 PAGES
OF 32 BYTES
Slave Address/Direction Byte
To be individually accessed, each device must have a
slave address that does not conflict with other devices
on the bus. The slave address to which the DS28CN01
responds is shown in Figure 1. The slave address is
part of the slave-address/direction byte. The upper 3
bits of the DS28CN01 slave address are set to 101b.
The AD0 pin controls address A0 and A1; AD1 controls
A2 and A3. AD0 and AD1 can be connected to GND,
V
CC
, SCL, or SDA. Table 1 shows the translation of
these four pin states to binary addresses. To be select-
ed, the device must be addressed with A0 to A3 match-
ing the binary address of the respective pins.
The last bit of the slave-address/direction byte (R/W)
defines the data direction. When set to a 0, subsequent
data flows from master to slave (write-access mode);
when set to a 1, data flows from slave to master (read-
access mode).
Table 1. Pin State to Binary Translation
7-BIT SLAVE ADDRESS
AD1
A6
1
A5
0
A4
1
A3
AD1
A2
A1
AD0
A0
R/W
A3
0
0
1
1
A2
0
1
0
1
AD0
GND
V
CC
SCL
SDA
A1
0
0
1
1
A0
0
1
0
1
GND
V
CC
SCL
SDA
MSB
4-LEVEL PIN STATES
(SEE THE
SLAVE
DETERMINES
ADDRESS/DIRECTION
READ OR WRITE
BYTE
SECTION)
Figure 1. Slave Address
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5