Rev 1; 010809
DS33M30/DS33M31/DS33M33
Ethernet Over SONET/SDH Mapper
________________________ General Description
The DS33M30 family of products provides a compact
and efficient solution for transporting Gigabit Ethernet
traffic over OC-3/STM-1 optical networks. With the
addition of an optical transceiver, Ethernet PHY,
DDR SDRAM, and host processor, a complete
solution of GbE over OC-3/STM-1 can be
implemented. The family supports Ethernet over
SONET/SDH (EoS) at VC-4, “Next-Generation” EoS
high-order mapping with multiple concatenated
VC-3s, and Ethernet over PDH over SONET/SDH
(EoPoS) with up to three virtually concatenated
DS3/E3
tributaries.
The
supported
frame
encapsulations include GFP-F, HDLC, cHDLC, and
X.86 (LAPS).
_____________________________________Features
Support for EoS in One STS-3c/VC-4, EoS
Over Up to Three Concatenated STS-1/VC-3s,
and EoPoS Over Up to Three Concatenated
DS-3s
♦
Two Independent 155.52Mbps SerDes Ports
♦
One 10/100/1000 IEEE 802.3 Ethernet MAC
Port
♦
Configurable MII/RMII/GMII MAC Interface
♦
GFP/LAPS/HDLC/cHDLC Encapsulation
♦
IEEE 802.1Q VLAN and Q-in-Q Support
♦
Add/Drop OAM Frames from
µP
Interface
♦
Quality of Service (QoS) Support
♦
Traffic Policing Through CIR/CBS
♦
Classification Through PCP or DSCP
♦
Supports Up to 512Mb DDR SDRAM Buffer
♦
SPI and Parallel Microprocessor Interfaces
♦
1.8V, 2.5V, 3.3V Supplies
Features continued in Section
1.
♦
_______________________________ Applications
Ethernet Service Delivery Over SONET/SDH
Multiservice Provisioning Platforms (MSPPs)
Transparent LAN Services
LAN Extension
_________________________ Functional Diagram
DS33M30/M31/M33
SERDES A
Framer A
GFP / HDLC / LAPS
Advanced OAM
1 VC-4
High-Order
Mapper
3x VC-3
SERDES B
3
DS3/E3
Framers
Framer B
3
SerDes B AND FRAMER B ON
(DS33M31/33 ONLY)
DS3 ADD/DROP (DS33M33 ONLY)
____________________________________________________________ Ordering Information/Selector Guide
PART
DS33M30N+
DS33M31N+
DS33M33N+
SUPPORTED EoS/EoPoS
MODES
EoS at VC-4
EoS at VC-4,
EoS at 3xVC-3,
EoPoS at 3xDS3
EoS at VC-4,
EoS at 3xVC-3,
EoPoS at 3xDS3
155Mbps PORTS
1
2
2
EXT. DS3/E3 LINE
No
No
Yes (3)
PIN-PACKAGE
144 CSBGA
256 CSBGA
256 CSBGA
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ethernet MAC
Traffic Mgmt
VCAT /
LCAS
DS33M30/M31/M33 DATA SHEET
Table of Contents
1.
1.1
1.2
1.3
GENERAL DESCRIPTION AND FEATURE HIGHLIGHTS ........................................................... 4
D
EVICE
F
EATURE
O
VERVIEW
........................................................................................................ 5
TDM F
EATURE
O
VERVIEW
............................................................................................................ 6
SONET/SDH............................................................................................................................... 7
STS-3/STM-1 SerDes ....................................................................................................................... 7
STS-3/STM-1 Framer and Formatter ................................................................................................. 7
STS-3c/AU-4 Pointer Processing ...................................................................................................... 8
STS-3c SPE/VC-4 Path Termination ................................................................................................. 8
STS-3 Mux/Demux (DS33M31 and DS33M33 Only).......................................................................... 8
STS-1/AU-3/TU-3 Formatter and Framer (DS33M31 and DS33M33 Only)......................................... 9
STS-1/AU-3/TU-3 Pointer Processing (DS33M31 and DS33M33 only) .............................................. 9
STS-1/VC-3 Path Termination (DS33M31 and DS33M33 only)........................................................ 10
Add/Drop DS3/E3 Framer/Formatter (DS33M31 and DS33M33 only) .............................................. 12
DS3/E3 Ethernet Mapping (DS33M31 and DS33M33 only) ............................................................. 13
Line DS3/E3 Framer/Formatter (DS33M33 only) ............................................................................. 13
Loopback ........................................................................................................................................ 14
SONET/SDH VCAT/LCAS .............................................................................................................. 14
PDH VCAT/LCAS ........................................................................................................................... 15
GFP-F Encapsulation (per ITU-T G.7041) ....................................................................................... 15
HDLC Encapsulation ....................................................................................................................... 15
cHDLC Encapsulation ..................................................................................................................... 15
X.86 Encapsulation Support ............................................................................................................ 15
1.4
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4.1
1.4.2
1.4.3
1.4.4
1.5.1
1.5.2
1.6.1
1.6.2
1.6.3
1.6.4
1.7.1
1.7.2
1.7.3
1.7.4
1.7.5
1.7.6
1.7.7
PDH (DS33M31
AND
DS33M33 O
NLY
) ...................................................................................... 12
1.5
1.6
V
IRTUAL
C
ONCATENATION
(VCAT) (DS33M31
AND
DS33M33
ONLY
) ........................................... 14
E
NCAPSULATION
........................................................................................................................ 15
1.7
E
THERNET
F
EATURE
O
VERVIEW
.................................................................................................. 15
Ethernet MAC Interface................................................................................................................... 16
Ethernet Bridging for 10/100............................................................................................................ 16
Ethernet Traffic Classification .......................................................................................................... 16
Ethernet Traffic Profiling and Policing .............................................................................................. 16
Ethernet Traffic Scheduling ............................................................................................................. 16
Ethernet Control Frame Processing................................................................................................. 16
Q-in-Q............................................................................................................................................. 16
1.8 SDRAM I
NTERFACE
................................................................................................................... 16
1.9 C
LOCK
R
ATE
A
DAPTER
(CLAD) .................................................................................................. 16
1.10
SPI S
ERIAL
M
ICROPROCESSOR
F
EATURES
............................................................................... 17
1.11
P
ARALLEL
M
ICROPROCESSOR
I
NTERFACE
(DS33M31
AND
DS33M33 O
NLY
) ............................. 17
1.12
T
EST AND
D
IAGNOSTICS
.......................................................................................................... 17
2.
STANDARDS COMPLIANCE...................................................................................................... 18
3.
4.
APPLICATIONS .......................................................................................................................... 20
REVISION HISTORY ................................................................................................................... 21
Rev: 010809
2 of 21
DS33M30/M31/M33 DATA SHEET
List of Figures
Figure 1-1 TDM Functional Blocks ......................................................................................................................... 6
Figure 3-1. Example Application 1: EoS for DS33M30 .......................................................................................... 20
Figure 3-2. Example Application 2: EoPoS for DS33M31 Interworking with EoP in DS33X162 Family of Devices . 20
Figure 3-3. Example Application 3: EoPoS Transport for DS33M33 with Integrated Ethernet and PDH Services... 20
List of Tables
Table 1-1. Product Selection Matrix........................................................................................................................ 5
Table 1-2. Summary of Mapping Functions ............................................................................................................ 5
Table 2-1. Standards Compliance Summary ........................................................................................................ 18
Rev: 010809
3 of 21
DS33M30/M31/M33 DATA SHEET
1. General Description and Feature Highlights
The DS33M30 family of devices provides interconnection and mapping functionality between Ethernet and
SONET/SDH networking elements. The product family includes three devices with differing features:
•
•
•
DS33M30: One GMII mapped to STS-3c/VC-4 in a compact 10mm package.
DS33M31: One GMII/MII mapped to a protected interface, with higher order EoS and EoPoS.
DS33M33: One GMII/MII mapped to a protected interface, with higher order EoS, EoPoS and DS3/E3
add/drop mux.
All devices in the product family contain an Ethernet MAC port, one or two STS-3/STM-1 SerDes ports with the
LVDS/LVPECL interface, one or three GFP-F/HDLC/cHDLC/X.86 (LAPS) protocol encapsulators, one or three
higher order SONET/SDH mappers, a DDR SDRAM interface, and a local bus port for control/status. Ethernet
traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) protocol to be transmitted onto the STS-3/
STM-1 interface. The family receives encapsulated Ethernet frames from the SerDes receiver interface and
transmits the de-encapsulated frames onto the Ethernet port.
With the smallest footprint, the DS33M30 contains the smallest feature set in the product family. It performs EoS
higher order mapping of Ethernet frames into a single STS-3c SPE or VC-4. The DS33M30 has one 1000Mbps
(GbE) port with GMII interface. The DS33M30 supports Ethernet OAM insert/extract capability, QoS Priority
Scheduling, VLAN processing, and committed information rate (CIR)-based policers for the delivery of carrier
Ethernet services.
The DS33M31 and DS33M33 expand on the features of the DS33M30 with additional mapping capabilities. They
support next-generation Ethernet over SONET/SDH in virtually concatenated higher order containers as well as
Ethernet-over-PDH-over-SONET/SDH (EoPoS) at the DS3/E3 level. They have an Ethernet interface that can be
configured as a 10/100Mbps MII/RMII port or a 1000Mbps (GbE) GMII port. They integrate four
mapping/demapping functions:
•
•
•
•
SONET/SDH mapping: STS-1/VC-3 to STS-3/STM-1; or TU-3 to VC-4 to STM-1
PDH mapping: DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4);
EoS higher order mapping: Ethernet to STS-1/VC-3 (or TU-3); and
EoPoS mapping: Ethernet to DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4).
At the STS-3/STM-1 side, the DS33M31 and DS33M33 devices interface to an STS-3/STM-1 signal through dual
serial-data buses operating at the rate of 155.52Mbps. This allows the implementation of a protected SONET/SDH
at PHY layer. Each serializer/deserializer (SerDes) is supported with independent STS-3/STM-1 framer.
The DS33M33 supports all the features of the DS33M30 and DS33M31, with additional line interfaces for up to
three add/drop DS3/E3 tributaries.
The SerDes interfaces, with LVDS/LVPECL, can be seamlessly connected to commercially available optical
transceivers.
Microprocessor control can be accomplished through an 8/16-bit local bus or SPI bus. The family contains a
125MHz DDR SDRAM controller and interfaces to a 32-bit-wide 256Mb DDR SDRAM through a 16-bit data bus.
The DDR SDRAM is used to buffer data through the Ethernet and STS-3/STM-1 ports.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.
Rev: 010809
4 of 21
DS33M30/M31/M33 DATA SHEET
Table 1-1. Product Selection Matrix
PART
ETHERNET
PORT
STS-3/
STM-1
PORT
1
PDH
(DS3/E3)
PORT
0
ETHERNET
MAPPING
VLAN
PRIORITY
VCAT
µP
FORWARDING FORWARDING GROUPS
PACKAGE
CONTROL
SUPPORT
SUPPORT
(VCGS)
NA
Y
1
SPI
SPI or
Parallel
SPI or
Parallel
10mm, 144
CSBGA
17mm, 256
CSBGA
17mm, 256
CSBGA
DS33M30
1 GbE
EoS
2 (1+1
DS33M31 1 (10/100,
GbE)
protected)
2 (1+1
DS33M33 1 (10/100,
GbE)
protected)
0
EoS, EoPoS
Y
Y
3
3
EoS, EoPoS
Y
Y
3
Note:
The number of members for a VCG in the DS33M31 and DS33M33 can be 1, 2, or 3.
1.1
Device Feature Overview
Note: See the glossary section (in the full data sheet) for the descriptions of terms used in this
documentation, especially for the terms referring to the ports, blocks, and directions.
Table 1-2. Summary of Mapping Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
MAPPING FUNCTIONS “>”
Ethernet > STS-3c > STS-3
Ethernet > AU-4 > STM-1
Ethernet > STS-1 > STS-3
Ethernet > AU-3 > STM-1
Ethernet > TU-3 > AU-4 > STM-1
Ethernet > DS3 > STS-1 > STS-3
Ethernet > DS3 > AU-3 > STM-1
Ethernet > DS3 > TU-3 > AU-4 > STM-1
Ethernet > E3 > STS-1 > STS-3
Ethernet > E3 > AU-3 > STM-1
Ethernet > E3 > TU-3 > AU-4 > STM-1
DS3 > STS-1 > STS-3
DS3 > AU-3 > STM-1
DS3 > TU-3 > AU-4 > STM-1
E3 > STS-1 > STS-3
E3 > AU-3 > STM-1
E3 > TU-3 > AU-4 > STM-1
DS33M30
x
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS33M31
x
x
x
x
x
x
x
x
x
x
x
—
—
—
—
—
—
DS33M33
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
NOTES
—
—
—
—
—
Without
external DS3
port
Without
external E3
port
—
—
—
—
—
—
The DS33M30 family of devices offer the following features:
•
Supports the mapping protocols as listed in
Table 1-2.
•
Supports single 10/100/1000Mbps Ethernet interface
•
STS-3/STM-1 interface operating at 155.52Mbps
•
Supports two transmit timing modes for STS-3/STM-1 port(s):
•
Loop timing (transmit timing reference = receive timing)
•
Local timing (transmit timing reference = CLAD timing)
•
Supports three transmit timing modes for Line DS3/E3 ports: (DS33M33)
•
Loop timed (transmit timing reference = receive timing)
•
Line timed (or thru timed) (transmit timing reference = Drop DS3/E3 thru timing)
•
Local timed (transmit timing reference = CLAD timing)
•
Certain clock, data, and control signals can be inverted to allow a glueless interface to other devices
•
Certain port can be put into a low-power standby mode when not being used
Rev: 010809
5 of 21
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