19-4558; Rev 1; 3/10
3.3V Dual-Output LVPECL Clock Oscillator
General Description
The DS4625 is a dual-output, low-jitter clock oscillator
capable of producing frequency output pair combina-
tions ranging from 100MHz to 625MHz. The device
combines an AT-cut crystal, an oscillator, and a low-
noise phase-locked loop (PLL) in a 5.0mm x 3.2mm
surface-mount LCCC package. Standard frequency
options are listed in the
Ordering Information/Selector
Guide
table. For custom frequency options, contact the
factory at:
Custom.Oscillators@maxim-ic.com.
The DS4625 provides dual, low-voltage, positive emit-
ter-coupled logic (LVPECL) clock output drivers. The
output drivers can be enabled and disabled through
the OE pin, which is an active-high CMOS input that
has an internal pullup resistor. When high, both output
pairs are enabled.
The device operates from a single +3.3V ±10% supply.
The operating temperature range is -40°C to +85°C.
Features
♦
Standard Clock Output Frequencies: 100MHz,
125MHz, 150MHz, 156.25MHz, and 200MHz
♦
Phase Jitter < 0.7ps RMS (typical) from 12kHz to
20MHz
♦
LVPECL Output
♦
+3.3V ±10% Operating Voltage
♦
-40°C to +85°C Temperature Range
♦
Excellent Power-Supply Noise Rejection
♦
5.0mm x 3.2mm Ceramic LCCC Package
♦
Output Enable/Disable
DS4625
Applications
XGMII Clock Oscillator
InfiniBand
TM/SM
SAS/SATA
PCIe
®
1GbE/10GbE
Ordering Information/Selector Guide
PART
DS4625P+100/100
DS4625P+100/150
DS4625P+125/125
DS4625P+125/156
DS4625P+150/150
DS4625P+150/200
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
FREQUENCY (OP1:ON1)
(MHz) (f
C
)*
100.000
100.000
125.000
125.000
150.000
150.000
FREQUENCY (OP2:ON2)
(MHz) (f
C
)*
100.000
150.000
125.000
156.250
150.000
200.000
PIN-PACKAGE
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
10 LCCC
TOP
MARK
6AA
6AC
6BB
6BD
6CC
6CE
+Denotes
a lead(Pb)-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both
lead-based and lead-free soldering processes.
*Standard
frequency options. Contact the factory at
Custom.Oscillators@maxim-ic.com
for custom frequencies.
Pin Configuration and Typical Application Circuit appear at end of data sheet.
InfiniBand is a trademark and service mark of the InfiniBand Trade Association.
PCIe is a registered trademark of PCI-SIG Corp.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
3.3V Dual-Output LVPECL Clock Oscillator
DS4625
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to ground unless otherwise noted.)
Voltage Range on Any Pin Relative to Ground......-0.3V to +4.0V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
θ
JA
...................................................................+90°C/W (Note 1)
Storage Temperature Range ...............................-55°C to +85°C
Lead Temperature (soldering, 10s) .................................+260°C
Soldering Temperature (reflow) .......................................+260°C
Note 1:
Package thermal resistances were obtained using a two-layer board. For detailed information on package thermal consider-
ations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Operating Voltage Range
Input-Voltage High (OE)
Input-Voltage Low (OE)
SYMBOL
V
CC
V
IH
V
IL
CONDITIONS
MIN
2.97
0.7 x
V
CC
0
TYP
3.3
MAX
3.63
V
CC
0.3 x
V
CC
UNITS
V
V
V
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.97V to +3.63V, T
A
= -40°C to +85°C, typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Operating Current
SYMBOL
I
CC_PU
I
CC_PL
I
CC_OEZ
Output Frequency
Startup Time
Frequency Stability
Frequency Stability Over
Temperature with Initial
Tolerance
Initial Tolerance
Frequency Change Due to V
CC
Frequency Change Due to Load
Variation
Aging (15 Years)
OE Pullup Resistance
f
OUT1
f
OUT2
t
START
f
TOTAL/
f
C
CONDITIONS
LVPECL, output unloaded
LVPECL, output loaded
V
OE
= V
IL
V
OE
= V
IH
(Note 4)
Temperature, aging, load, supply, and
initial tolerance (Note 5)
V
CC
= +3.3V
-50
MIN
TYP
65
120
80
f
C
1.0
+50
MAX
90
140
115
UNITS
mA
mA
mA
MHz
ms
ppm
f
TEMP
/f
C
-35
±20
-3
±1
-7
+35
ppm
ppm
f
INITIAL
/f
C
V
CC
= +3.3V, T
A
= +25°C
f
VCC
f
LOAD
/f
C
f
AGING
/f
C
R
PU
T
A
= +25°C
V
CC
= +3.3V ±10%, T
A
= +25°C
±10% variation in termination resistance
+3
ppm/V
ppm
+7
100
130
ppm
k
70
2
_______________________________________________________________________________________
3.3V Dual-Output LVPECL Clock Oscillator
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.97V to +3.63V, T
A
= -40°C to +85°C, typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Output High Voltage
Output Low Voltage
Differential Output Voltage
Output Rise Time
Output Fall Time
Duty Cycle
Propagation Delay from OE
Going Low to Output High
Impedance
Propagation Delay from OE
Going High to Output Active
Jitter
Accumulated Deterministic
Jitter Due to Reference Spurs
Accumulated Deterministic
Jitter Due to Power-Supply Noise
(P-P) (Note 6)
SYMBOL
V
OH
V
OL
|V
OD
|
t
R
t
F
D
CYCLE
t
PAZ
(See Figure 2)
CONDITIONS
Output connected to 50
V
CC
- 2.0V
Output connected to 50
V
CC
- 2.0V
Output connected to 50
V
CC
- 2.0V
20% to 80%
80% to 20%
45
at PECL_BIAS at
at PECL_BIAS at
at PECL_BIAS at
MIN
V
CC
-
1.085
V
CC
-
1.825
0.595
0.710
200
200
55
100
TYP
MAX
V
CC
-
0.88
V
CC
-
1.62
UNITS
V
V
V
ps
ps
%
ns
DS4625
t
PZA
J
RMS
(See Figure 2)
Integrated phase RMS, 12kHz to 20MHz,
V
CC
= +3.3V, T
A
= +25°C
125.00MHz output, V
CC
= +3.3V,
T
A
= +25°C
10kHz
100kHz
200kHz
1MHz
0.7
0.1
12.9
26.3
20.1
6.4
100
ns
ps
ps
ps
ps
ps
ps
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Limits at -40°C are guaranteed by design and are not production tested.
AC parameters are guaranteed by design and not production tested.
Startup time is from V
CC
= V
CCMIN
until PLL locks to the crystal oscillator output.
Frequency stability is calculated as:
Δf
TOTAL
=
Δf
TEMP
+
Δf
VCC
x (3.3 x 10%) +
Δf
LOAD
+
Δf
AGING
.
Supply-induced jitter is the deterministic jitter as measured on a LeCroy SDA11000 measured with a 50mV
P-P
sine wave
forced on V
CC
.
SINGLE-SIDEBAND PHASE NOISE
SSB PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, +3.3V)
OFFSET
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
20MHz
f
C
= 100MHz
-71
-116
-119
-126
-143
-151
-151
f
C
= 125MHz
-85
-117
-118
-125
-142
-149
-150
f
C
= 150MHz
-84
-116
-116
-122
-141
-149
-149
f
C
= 156.25MHz
-79
-115
-117
-123
-140
-148
-149
f
C
= 200MHz
-85
-113
-113
-120
-139
-149
-150
dBc/Hz
UNITS
_______________________________________________________________________________________
3
3.3V Dual-Output LVPECL Clock Oscillator
DS4625
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
f
C
DEVIATION vs. TEMPERATURE
40
30
DEVIATION (ppm)
20
10
0
-10
-20
-30
-40
-50
-40
-20
0
20
40
60
TEMPERATURE (°C)
0
3.0
3.1
DS4625 toc01
f
C
DEVIATION vs. V
CC
DS4625 toc02
I
CC
vs. V
CC
130
120
I
CC_PU
DS4625 toc03
50
3.0
2.5
DEVIATION (ppm)
2.0
1.5
1.0
0.5
140
CURRENT (mA)
110
100
90
80
70
60
50
I
CC_PL
ONE OUTPUT LOADED
3.2
3.3
V
CC
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
V
CC
(V)
3.4
3.5
3.6
Pin Description
PIN
1
2, 3
4
5
6
A1, A2
A3
A4
—
NAME
OE
GND
OP1
ON1
V
CC
N.C.
OP2
ON2
EP
Ground
Positive Output 1 for LVPECL
Negative Output 1 for LVPECL
Supply Voltage Input
No Internal Connection. Must be connected to ground.
Positive Output 2 for LVPECL
Negative Output 2 for LVPECL
Exposed Pad. The exposed pad must be used for thermal relief. This pad must be connected to
ground.
FUNCTION
Active-High Output Enable. Has an internal pullup resistor (R
PU
).
4
_______________________________________________________________________________________
3.3V Dual-Output LVPECL Clock Oscillator
DS4625
V
CC
V
CC
R
PU
X1
OE
X0
PLL
LC-VCO
X2
PFD
LPF
DIV M
LVPECL
ON1
DIV N
OP2
OP1
DS4625
DIV P
LVPECL
ON2
GND
Figure 1. Block Diagram
0.7 x V
CC
OE
0.3 x V
CC
t
PZA
t
PAZ
OP_
PECL_BIAS
PECL_BIAS
ON_
PECL_BIAS
PECL_BIAS
Figure 2. LVPECL Output Timing Diagram When OE is Enabled and Disabled
_______________________________________________________________________________________
5
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