Rev 1; 2/09
HART Modem
General Description
The DS8500 is a single-chip modem with Highway
Addressable Remote Transducer (HART) capabilities
and satisfies the HART physical layer requirements.
The device integrates the modulation and demodulation
of the 1200Hz/2200Hz FSK signal, has very low power
consumption, and needs only a few external compo-
nents due to the integrated digital signal processing.
The input signal is sampled by an analog-to-digital con-
verter (ADC), followed by a digital filter/demodulator.
This architecture ensures reliable signal detection in
noisy environments. The output digital-to-analog con-
verter (DAC) generates a sine wave and provides a
clean signal with phase-continuous switching between
1200Hz and 2200Hz. Low power is achieved by dis-
abling the receive circuits during transmit and vice
versa. The DS8500 is ideal for low-power process con-
trol transmitters.
Features
♦
Single-Chip, Half-Duplex, 1200bps FSK
Modulation and Demodulation
♦
Digital Signal Processing Provides Reliable Input
Signal Detection in Noisy Conditions
♦
Sinusoidal Output Signal with Lowest Harmonic
Distortion
♦
Few External Components Enable a Space-Saving
Solution
♦
Standard Component 3.6864MHz Crystal
♦
Complies to HART Physical Layer Requirements
♦
2.7V to 3.6V Operating Voltage
♦
285µA (max) Current Consumption
♦
Space-Saving, 5mm x 5mm x 0.8mm, 20-Pin TQFN
Package
DS8500
Applications
4–20mA Loop-Powered Transmitters for
Temperature, Pressure, Flow, and Level
Measurement
HART Multiplexers
HART Modem Interface Connectivity
Ordering Information
PART
DS8500-JND+
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
20 TQFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Pin Configuration
AGND
REF
AVDD
11
TOP VIEW
15
14
13
12
DGND 16
DGND 17
DGND 18
D_OUT 19
D_IN 20
DS8500
FSK_OUT
FSK_IN
10
9
8
7
XCEN
DGND
XTAL2
XTAL1
RTS
+
1
DVDD
2
DVDD
3
DGND
4
RST
*EP
6
5
OCD
*EXPOSED PAD.
THIN QFN
(5mm
×
5mm)
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
HART Modem
DS8500
ABSOLUTE MAXIMUM RATINGS
Voltage Range on All Pins (including AVDD,
DVDD) Relative to Ground .................................-0.5V to +3.6V
Voltage Range on Any Pin Relative to
Ground Except AVDD, DVDD .............-0.5V to (V
DVDD
+ 0.5V)
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(V
DVDD
= V
AVDD
= 2.7V to 3.6V, T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Digital Supply Voltage
Analog Supply Voltage
Ground
Digital Power-Fail Reset Voltage
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I/O Pin Capacitance
RST
Pullup Resistance
Input Leakage Current XTAL,
RST
Input Leakage Current All Other
Pins
Input Low Current for
RST
CLOCK SOURCE
External Clock Frequency
VOLTAGE REFERENCE
Internal Reference Voltage
FSK INPUT
Input Voltage Range at FSK_IN
FSK OUTPUT
Output Voltage at FSK_OUT
Frequency of FSK_OUT (Note 4)
V
OUT
AC-coupled max 30k
For a mark
For a space
load
400
-1%
-1%
500
1200
2200
600
+1%
+1%
mV
P-P
Hz
0
V
REF
V
V
REF
1.23
V
f
HFIN
-1%
3.6864
+1%
MHz
SYMBOL
V
DVDD
V
AVDD
GND
V
RST
I
DD
V
IL
V
IL
V
OL
V
OH
C
IO
R
RST
I
ILRX
I
IL
I
IL1
V
IN
= 0.4V
I
OL
= 4mA
I
OH
= -4mA
Guaranteed by design (Note 3)
19
-30
-2
V
AVDD
= V
DVDD
AGND = DGND
Monitors V
DVDD
V
AVDD
= V
DVDD
= 2.7V (Note 2)
DGND
0.75 x
V
DVDD
DGND
0.8 x
V
DVDD
15
45
+30
+2
170
CONDITIONS
MIN
2.7
2.7
0
2.59
2.64
TYP
MAX
3.6
3.6
0
2.69
285
0.30 x
V
DVDD
V
DVDD
0.4
UNITS
V
V
V
V
μA
V
V
V
V
pF
k
μA
μA
μA
Note 1:
Note 2:
Note 3:
Note 4:
2
Specifications to -40°C are guaranteed by design and are not production tested.
Active currents are measured when the device is driven by an external clock XCEN = 1 condition.
Guaranteed by design and not production tested.
Accuracy is guaranteed based on the external crystal or clock provided.
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HART Modem
Pin Description
PIN
1, 2
3, 9, 16,
17, 18
4
NAME
DVDD
DGND
RST
Digital Supply Voltage
Digital Ground
Active-Low Reset, Digital Input/Output. This pin includes an internal pullup resistor and is driven low
as an output when an internal reset condition occurs.
Carrier Detect, Digital Output. A logic-high indicates a valid carrier detection on FSK_IN.
OCD = 1 when FSK_IN amplitude is greater than 120mV
P-P
.
OCD = 0 when FSK_IN amplitude is less than 80mV
P-P
.
Request to Send, Digital Input. When set high, the device is put into the demodulator mode. A logic-low
puts the device into modulator mode.
Crystal Pin or Input for External Clock at 3.6864MHz
Crystal Pin or Output of the Crystal Amplifier
External Clock Enable, Digital Input. When set high, this pin allows the user to drive an external clock
signal through XTAL1. When in this mode, XTAL2 should be left unconnected. An external crystal must
be connected between XTAL1 and XTAL2 when set low.
Analog Supply Voltage
FSK Out, Analog Output. Output of the modulator. Provides a phase-continuous, FSK-modulated output
signal (1200Hz and 2200Hz output frequencies) to the 4–20mA current loop interface circuit.
Reference, Analog Output. The internal voltage reference is provided as output. This pin must be
connected to a 0.1μF capacitor.
FSK In, Analog Input. Input for the FSK-modulated HART receive signal from the 4–20mA current loop
interface circuit.
Analog Ground
Digital Data Out, Digital Output. Output from the demodulator.
Digital Data In, Digital Input. Input to the modulator.
Exposed Pad. Should be connected to ground (DGND, AGND).
FUNCTION
DS8500
5
OCD
6
7
8
10
11
12
13
14
15
19
20
—
RTS
XTAL1
XTAL2
XCEN
AVDD
FSK_OUT
REF
FSK_IN
AGND
D_OUT
D_IN
EP
Block Diagram
RST
DVDD DGND
AGND
AVDD
XTAL1
XTAL2
XCEN
OCD
D_OUT
RTS
D_IN
CRYSTAL
OSCILLATOR
CLOCK
GENERATOR
POWER
MONITOR
V
REF
1.23V
REF
Rx
DEMODULATOR
Tx
MODULATOR
DIGITAL
FILTER
SAMPLE/HOLD
ADC
FSK_IN
DAC
DS8500
FSK_OUT
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3
HART Modem
DS8500
Introduction to HART
HART is a backward-compatible enhancement to exist-
ing 4–20mA instrumentation networks that allows two-
way, half-duplex, digital communication with a
microcontroller-based field device. The digital signal is
encoded on top of the existing instrumentation signal.
Communication is accomplished through a series of
commands and responses dependent on the specific
protocol and network topology. The DS8500 does not
implement any portion of the communication protocol; it
only handles the modulation and demodulation of the
encoded information. Digital data is encoded using fre-
quency-shift keying (FSK), which is illustrated in Figure
1. A “1” is identified as a mark symbol and is represent-
ed with a center frequency of 1.2kHz. A “0” is identified
as a space symbol and is represented with a center fre-
quency of 2.2kHz. This allows a throughput of 1.2kbps,
with each symbol occupying an 833µs slot.
chip; the attenuated signal is digitized by the ADC and
filtered by the receive state machine. The transmit state
machine modulates the input to the HART-compliant
signal with the help of the modulator and the DAC.
Modulator
The modulator performs the FSK modulation of the digi-
tal data at the D_IN input. The FSK-modulated sinu-
soidal signal is present at the FSK_OUT output as
illustrated in Figure 1. The modulator is enabled by RTS
being a logic-low. The modulation is done between
1200Hz (mark) or 2200Hz (space) depending on the
logic level of the input signal. The modulator preserves a
continuous phase when switching between frequencies
to minimize the bandwidth of the transmitted signal.
Figure 2 illustrates an example waveform of the DS8500
in modulate mode. The data to be modulated is pre-
sented in a UART format (start, 8 data bits, parity, stop
bit) at D_IN. FSK_OUT shows the modulated output.
Demodulator
V
T
The demodulator accepts an FSK signal at the FSK_IN
input and reproduces the original modulating signal at
the D_OUT output. The HART signal should be present-
ed as an 11-bit UART character with a start, data, pari-
ty, and stop bits for proper operation of the
demodulator block. The nominal bit rate of the D_OUT
signal is 1200 bits per second. A simple RC filter is suf-
ficient for anti-aliasing. Figure 3 illustrates an example
waveform of the DS8500 in demodulate mode.
Applications Information
1.2kHz MARK
"1"
2.2kHz SPACE
"0"
Figure 1. HART FSK Signal
Functional Description
The DS8500 modem chip consists of a demodulator, car-
rier detect, digital filter, ADC for input signal conversion, a
modulator and DAC for output signal generation, and
receive and transmit state machine blocks to perform the
HART communication. The
Block Diagram
illustrates
the interface between various blocks of circuitry.
The input HART signal’s noise interference is attenuat-
ed by a one-pole highpass filter that is external to the
Figure 4 shows the typical application circuit. As the
DS8500 integrates a digital filter, only a simple passive
RC filter is required in front of the ADC. R3 and C3
implement a lowpass filter with a 10kHz cutoff frequen-
cy; C2 and R2/R1 implement a highpass filter with a
480Hz cutoff frequency. The resistor-divider formed by
R1 and R2 provides an input bias voltage of V
REF
/2 to
the ADC input (R1 = R2).
The output DAC provides a sine-wave signal, and C4
provides the AC-coupled signal output from the
DS8500. The typical value of C4 can be anything
greater than 20nF based on the application.
Technical Support
For technical support, go to
http://support.maxim-
ic.com/micro.
4
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HART Modem
DS8500
1200bps/833μs
D_IN
STOP
START
8-BIT DATA
PARITY
FSK_OUT
Figure 2. Actual DS8500 Modulator Waveform
FSK_IN
START
D_OUT
8-BIT DATA
STOP
PARITY
1200bps/833μs
ONE UART CHARACTER (START, 8 DATA BITS, PARITY, STOP)
Figure 3. Actual DS8500 Demodulator Waveform
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