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C1632C562M3RAC

Description
ISOLATED C NETWORK, 25V, X7R, 0.0056uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT
CategoryPassive components    capacitor   
File Size777KB,2 Pages
ManufacturerKEMET
Websitehttp://www.kemet.com
Environmental Compliance  
Download Datasheet Parametric View All

C1632C562M3RAC Overview

ISOLATED C NETWORK, 25V, X7R, 0.0056uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT

C1632C562M3RAC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerKEMET
package instructionCHIP,
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance0.0056 µF
Capacitor typeARRAY/NETWORK CAPACITOR
JESD-609 codee3
length3.2 mm
Manufacturer's serial numberC
Installation featuresSURFACE MOUNT
negative tolerance20%
Network TypeISOLATED C NETWORK
Number of components1
Number of functions4
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
encapsulated codeCHIP
Package shapeRECTANGULAR PACKAGE
positive tolerance20%
Rated (DC) voltage (URdc)25 V
Maximum seat height1.35 mm
surface mountYES
Temperature characteristic codeX7R
Temperature Coefficient15% ppm/°C
Terminal surfaceTin (Sn) - with Nickel (Ni) barrier
Terminal pitch0.8 mm
Terminal shapeWRAPAROUND
width1.6 mm
CERAMIC CAPACITOR ARRAY
FEATURES
Four individual capacitors inside
one 1206 monolithic structure
Saves board and inventory space
One placement instead of four - less costly
Easier to handle and solder than 4 smaller chips
Tape and reel per EIA 481-1
RoHS Compliant
CAPACITOR OUTLINE DRAWING
T
L
CL
BW
W
P/2
Ref
P
BW1
TABLE 1
EIA DIMENSIONS – MILLIMETERS (INCHES)
Size
Code
1632
Length
L
3.2 (0.126)
±
0.2 (0.008)
Width
W
1.6 (.063)
±
0.2 (.008)
Thickness
T (max.)
0.7 - 1.35
(0.027 - 0.053)
Bandwidth
BW
Bandwidth
BW1
Pitch
P
0.40 (0.016)
0.1 - 0.5
0.8 (0.031)
±
0.2 (0.008) (0.004 - 0.020)
±
0.1 (0.004)
Notes:
1. Metric is controlling - English for reference only.
2. Pitch (P) tolerances are non-cumulative along the package.
3. Thickness (T) depends on capacitance.
CERAMIC ARRAY ORDERING INFORMATION
C
1632
C
103
K
5
R
A
C
END METALLIZATION
C-Standard
(Tin-plated nickel barrier)
FAILURE RATE LEVEL
A- Not Applicable
TEMPERATURE CHARACTERISTIC
Designated by Capacitance
Change Over T
emperature Range
G – C0G (NP0) (±30 PPM/°C)
R – X7R (±15%)
VOLTAGE
5 = 50v; 3 = 25v; 4 = 16v; 8=10v
CERAMIC
EIA SIZE CODE
Ceramic chip array
SPECIFICATION
C - Standard
CAPACITANCE CODE
Expressed in Picofarads (pF)
First two digits represent significant figures.
Third digit specifies number of zeros. (Use 9
for 1.0 thru 9.9pF (Example: 2.2pF = 229
.
CAPACITANCE TOLERANCE
K –
±10%:
M –
±20%
Standard Tolerances
Contact factory for any special requirements.
84
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
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