MT57W2MH18JF-3 datasheet, PDF - EEWORLD Datasheet

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MT57W2MH18JF-3: DescriptionDDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165; Categorystorage storage; File Size347KB，28 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT57W2MH18JF-3 Overview

DDR SRAM, 2MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, FBGA-165

MT57W2MH18JF-3 Parametric

Parameter Name	Attribute value
Maker	Micron Technology
Parts packaging code	BGA
package instruction	TBGA,
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	37748736 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX18
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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ADVANCE

‡

4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36

1.8V V

, HSTL, DDRIIb4 SRAM

36Mb DDRII CIO SRAM

4-WORD BURST

Features

•

DLL circuitry for accurate output data placement

Pipelined double data rate operation

Common data input/output bus

Fast clock to valid data times

Full data coherency, providing most current data

Four-tick burst counter for reduced-address latency

Two input clocks (K and K#) for precise DDR timing

at clock rising edges only

Two output clocks (C and C#) for precise flight time

and clock skew matching—clock and data delivered

together to receiving device

Optional-use echo clocks (CQ and CQ#) for flexible

receive data synchronization

Simple control logic for easy depth expansion

Internally self-timed, registered writes

Core V

= 1.8V (±0.1V); I/O V

Q = 1.5V to V

(±0.1V) HSTL

Clock-stop capability with µs restart

15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA

package

User-programmable impedance output

JTAG boundary scan

MT57W4MH8J

MT57W4MH9J

MT57W2MH18J

MT57W1MH36J

Figure 1: 165-Ball FBGA

•

Table 1:

Valid Part Numbers

DESCRIPTION

4 Meg x 8, DDRIIb4 FBGA

4 Meg x 9, DDRIIb4 FBGA

2 Meg x 18, DDRIIb4 FBGA

1 Meg x 36, DDRIIb4 FBGA

PART NUMBER

MT57W4MH8JF-xx

MT57W4MH9JF-xx

MT57W2MH18JF-xx

MT57W1MH36JF-xx

Options

• Clock Cycle Timing

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200 MHz)

6ns (167 MHz)

7.5ns (133 MHz)

• Configurations

4 Meg x 8

4 Meg x 9

2 Meg x 18

1 Meg x 36

• Package

165-ball, 15mm x 17mm FBGA

NOTE:

Marking

-3

-3.3

-4

-5

-6

-7.5

MT57W4MH8J

MT57W4MH9J

MT57W2MH18J

MT57W1MH36J

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

The Micron

DDRII synchronous, pipelined burst

SRAM employs high-speed, low-power CMOS designs

using an advanced 6T CMOS process.

The DDR SRAM integrates an SRAM core with

advanced synchronous peripheral circuitry and a two-

bit burst counter. All synchronous inputs pass through

registers controlled by an input clock pair (K and K#)

and are latched on the rising edge of K and K#. The

synchronous inputs include all addresses, all data

inputs, active low load (LD#), read/write (R/W#), and

active LOW byte writes or nibble writes (BWx# or

NWx#). Write data is registered on the rising edges of

both K and K#. Read data is driven on the rising edge of

C and C#, if provided, or on the rising edge of K and K#

if C and C# are not provided.

General Description

36Mb: 1.8V V

, HSTL, DDRIIb4 SRAM

MT57W1MH36J_B.fm – Rev. B, Pub. 2/03

‡

PRODUCTS

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

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