MT5VDDT1672AY-262XX datasheet, PDF

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MT5VDDT1672AY-262XX: DescriptionDDR DRAM Module, 16MX72, 0.75ns, CMOS, LEAD FREE, DIMM-184; Categorystorage storage; File Size589KB，29 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT5VDDT1672AY-262XX Overview

DDR DRAM Module, 16MX72, 0.75ns, CMOS, LEAD FREE, DIMM-184

MT5VDDT1672AY-262XX Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	184
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N184
JESD-609 code	e4
memory density	1207959552 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	30

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64MB, 128MB, 256MB (x72, ECC, SR)

184-PIN DDR SDRAM UDIMM

DDR SDRAM

UNBUFFERED DIMM

Features

• JEDEC-standard 184-pin, dual in-line memory

module (DDR DIMM)

• Utilizes 266 MT/s and 333MT/s DDR SDRAM

components

• Fast data transfer rates: PC2100 or PC2700

• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and

256MB (32 Meg x 72)

• Supports ECC error detection and correction

• V

= V

Q = +2.5V

• V

DDSPD

= +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data—i.e., source-synchronous data

capture

• Differential clock inputs (CK and CK#)

• Four internal device banks for concurrent operation

• Selectable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 15.625µs (64MB); 7.8125µs (128MB, 256MB)

maximum average periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Selectable READ CAS latency for maximum

compatibility

• Gold edge contacts

MT5VDDT872A – 64MB

MT5VDDT1672A – 128MB

MT5VDDT3272A – 256MB

For the latest data sheet, please refer to the Micron



Web

site:

www.micron.com/products/modules

Figure 1: 184-Pin DIMM (MO-206)

OPTIONS

MARKING

• Package

184-pin DIMM (standard)

184-pin DIMM (lead-free)

• Memory Clock, Speed, CAS Latency (CL)

6ns, 333 MT/s (167 MHz), CL = 2.5

-335

7.5ns, 266 MT/s (133 MHz), CL = 2

-262

7.5ns, 266 MT/s (133 MHz), CL = 2

-26A

7.5ns, 266 (133 MHz), CL = 2.5

-265

• Self Refresh

Standard

None

Low Power

NOTE:

1. Consult Micron for product availability.

2. CL = Device CAS (READ) Latency.

Table 1:

Address Table

64MB

128MB

8K (A0 –A12)

4 (BA0, BA1)

256Mb (16 Meg x 16)

512 (A0 –A8)

1 (S0#)

256MB

8K (A0 –A12)

4 (BA0, BA1)

512Mb (32 Meg x 16)

1K (A0 –A9)

1 (S0#)

4K (A0 –A11)

4 (BA0, BA1)

128Mb (8 Meg x 16)

512 (A0 –A8)

1 (S0#)

Refresh Count

Row Addressing

Device Bank Addressing

Device Configuration

Column Addressing

Module Rank Addressing

pdf: 09005aef808143d9, source: 09005aef806e1c40

DD5C8_16_32x72AG.fm - Rev. E 9/04 EN

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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