K4S56163LC-R(B)F/R
4M x 16Bit x 4 Banks Mobile SDRAM in 54CSP
FEATURES
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1 & 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. TCSR (Temperature Compensated Self Refresh).
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70
°C).
• 54balls CSP (-RXXX - Pb, -BXXX - Pb Free).
K4S56163LC-R(B)F/R75
K4S56163LC-R(B)F/R1H
K4S56163LC-R(B)F/R1L
K4S56163LC-R(B)F/R15
CMOS SDRAM
GENERAL DESCRIPTION
The K4S56163LC is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock and I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst length
and programmable latencies allow the same device to be useful for
a variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
Part No.
Max Freq.
133MHz(CL=3)
105MHz(CL=2)
105MHz(CL=2)
105MHz(CL=3)
*1
66MHz(CL=2/3)
*2
Interface Package
54 CSP
LVCMOS
Pb
(Pb Free)
-R(B)R ; Super Low Power, Operating Temperature ; -25°C~85°C.
-R(B)F ; Low Power, Operating Temperature ; -25
°C~85 °C.
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. In case of 33MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
Bank Select
4M x 16
Sense AMP
4M x 16
4M x 16
4M x 16
LDQM
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 Dec. 2002
K4S56163LC-R(B)F/R
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
D D
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T = -25°C to 70
°C)
A
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
D D
V
DDQ
V
I H
V
IL
V
O H
V
OL
I
LI
Min
2.3
1.65
0.8 x V
DDQ
-0.3
V
DDQ
-0.2
-
-10
Typ
2.5
-
-
0
-
-
-
Max
2.7
2.7
V
DDQ
+ 0.3
0.3
-
0.2
10
Unit
V
V
V
V
V
V
uA
1
2
I
O H
= -0.1mA
I
OL
= 0.1mA
3
Note
Notes :
1. V
IH
(max) = 3.0V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -1.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
(V
D D
= 2.5V, T
A
= 23
°C,
f = 1MHz, V
REF
Pin
Clock
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
15
Symbol
C
CLK
C
IN
C
ADD
C
OUT
=0.9V
±
50 mV)
Min
2.0
2.0
2.0
3.5
Max
4.0
4.0
4.0
6.0
Unit
pF
pF
pF
pF
Note
Rev. 1.4 Dec. 2002
K4S56163LC-R(B)F/R
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -25°C to 70°C)
Parameter
Symbol
Burst length = 1
t
RC
≥
t
R C
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
Test Condition
-75
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
I
CC1
75
CMOS SDRAM
Version
-1H
70
-1L
65
-15
60
Unit
Note
mA
1
I
CC2
P
0.5
0.5
15
I
C C 2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
mA
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
I
CC3
P
mA
10
6
6
25
mA
I
C C 3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
C C D
= 2CLKs
t
RC
≥
t
R C
(min)
TCSR Range
4 Banks
-R(B)F
2 Banks
1 Bank
4 Banks
-R(B)R
2 Banks
1 Bank
mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
NS
25
mA
Operating Current
(Burst Mode)
Refresh Current
I
CC4
115
95
95
85
mA
1
I
CC5
165
155
150
125
mA
°C
2
Max 45°C
500
400
350
360
260
200
Max 70°C
750
550
420
630
430
300
3
uA
4
Self Refresh Current
I
CC6
CKE
≤
0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S56163LC-R(B)F**
4. K4S56163LC-R(B)R**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 1.4 Dec. 2002
Electronics Design Contest
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