Less than 200pS cycle-to-cycle jitter is compatible
with Pentium
®
based systems
Available in 16pin, 150mil SOIC, 4.4mm TSSOP
(ASM3P623S09A/B), and in 8pin, 150 mil SOIC,
4.4mm TSSOP Packages (ASM3P623S05A/B)
•
•
•
3.3V Operation
Advanced CMOS technology
The First True Drop-in Solution
the eight-pin version and accepts one reference input and
drives out five low-skew clocks.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S05/09A/B devices can accept the
same input clock and distribute it. In this case, the skew
between the outputs of the two devices is guaranteed to be
less than 700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than
±350pS,
and the output-to-output skew is
guaranteed to be less than 250pS.
Refer
“
Spread Spectrum Control and Input-Output Skew
Functional Description
ASM3P623S05/09A/B is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed Timing-Safe™ clocks
with Peak EMI Reduction. ASM3P623S09A/B accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16pin Package. The ASM3P623S05A/B is
Table”
for
deviations
and
Input-Output
Skew
for
ASM3P623S05A/B and ASM3P623S09A/B devices
The
ASM3P623S05A/B
and
ASM3P623S09A/B
are
available in two different packages, as shown in the
ordering information table.
Block Diagram
CLKIN
PLL
CLKOUT
CLKIN
CLK1
CLK2
CLK3
PLL
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
ASM3P623S05A/B
CLK4
S2
S1
Select Input
Decoding
CLKB1
CLKB2
CLKB3
ASM3P623S09A/B
CLKB4
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2007
rev 0.3
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
ASM3P623S05/09A/B
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating
the
clock
frequency.
The
ASM3P623S05/09A/B uses the center modulation spread
spectrum technique in which the modulated output
frequency varies above and below the reference
frequency with a specified modulation rate. With center
modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Pin Configuration ( 8 Pin Devices )
CLKIN
1
8
7
6
5
CLKOUT
CLK4
V
DD
CLK3
CLK1
2
CLK2
3
GND
4
ASM3P623S05A/B
Pin Configuration ( 16 Pin Devices )
CLKIN
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
ASM3P623S09A/B
13
12
11
10
9
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 15
May 2007
rev 0.3
Pin Description for ASM3P623S05A/B
Pin #
1
2
3
4
5
6
7
8
ASM3P623S05/09A/B
Pin Name
CLKIN
CLK1
1
CLK2
1
GND
CLK3
1
V
DD
CLK4
1
CLKOUT
1,2
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Description
Input reference frequency, 5V-tolerant input
Buffered clock output, internal feedback on this pin
Notes: 1. Weak pull-down on these outputs.
2. This output is driven and has an internal feedback for the PLL.
3. Buffered clock output is Timing-Safe™
Pin Description for ASM3P623S09A/B
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
CLKA1
1
CLKA2
1
V
DD
GND
CLKB1
S2
2
S1
2
CLKB3
1
CLKB4
1
GND
V
DD
CLKA3
1
CLKA4
1
CLKOUT
1,3
1
Description
Input reference frequency, 5V tolerant input
Buffered clock output
Buffered clock output
3.3V supply
Ground
Buffered clock output
Buffered clock output
Select Input, bit 2
Select Input, bit 1
Buffered clock output
Buffered clock output
Ground
3.3V supply
Buffered clock output
Buffered clock output
Buffered output, Internal feedback on this pin
CLKB2
1
Notes: 1. Weak pull-down on all outputs.
2. Weak pull-up on these Inputs.
3. This output is driven and has an internal feedback for the PLL.
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 15
May 2007
rev 0.3
Spread Spectrum Control and Input-Output Skew Table
(Note: The values given in the table are for an input frequency of 32MHz)
ASM3P623S05/09A/B
Device
ASM3P623S05A
ASM3P623S05B
ASM3P623S09A
ASM3P623S09B
Deviation
±0.25 %
±0.5 %
±0.25 %
±0.5 %
Input-Output Skew(±T
SKEW
)
0.125
0.25
0.125
0.25
Note: T
SKEW
is measured in units of the Clock Period
Absolute Maximum Ratings
Symbol
VDD
T
STG
T
s
T
J
T
DV
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
260
150
2
Unit
V
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions for ASM3P623S05A/B and ASM3P623S09A/B Devices
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
-40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
Electrical Characteristics for ASM3P623S05A/B and ASM3P623S09A/B
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
Description
Input LOW Voltage
1
Input HIGH Voltage
1
Input LOW Current
Input HIGH Current
Output LOW Voltage
2
Output HIGH Voltage
2
Supply Current
Output Impedance
V
IN
= 0V
Test Conditions
Min
2.0
Typ
Max
0.8
50
100
0.4
Unit
V
V
µA
µA
V
V
mA
Ω
V
IN
= V
DD
I
OL
= 8mA
I
OH
= -8mA
Unloaded outputs
2.4
15
23
Note: 1. CLKIN input has a threshold voltage of V
DD
/2
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 15
May 2007
rev 0.3
ASM3P623S05/09A/B
Switching Characteristics for ASM3P623S05A/B and ASM3P623S09A/B
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Description
Output Frequency
Duty Cycle
2
= (t
2
/ t
1
) * 100
Output Rise Time
1, 2
Output Fall Time
1, 2
Output-to-output skew
2
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
2
Test Conditions
30pF load
Measured at V
DD
/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
20
40
Typ
50
Max
50
60
2.5
2.5
250
±350
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Device-to-Device Skew
2
Cycle-to-cycle jitter
2
PLL Lock Time
2
Note: 1. The parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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