EEWORLDEEWORLDEEWORLD

Part Number

Search

ASM3P2474A

Description
Low Power Peak EMI Reducing Solution
File Size170KB,10 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Compare View All

ASM3P2474A Overview

Low Power Peak EMI Reducing Solution

October 2005
rev 1.0
Low Power Peak EMI Reducing Solution
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V Supply.
Operating current less than 6mA.
Low power CMOS design.
Input frequency range : 13MHz to 30MHz
Generates a 1X and 2X low EMI spread spectrum
clock of the input frequency.
Output Frequency Selection through FSEL pin
Frequency deviation : -1.5% (Typ) @25MHz
: -1.5% (Typ) @50MHz
Available in 6-pin TSOT-23, 8-pin SOIC and 8-pin
TSSOP packages.
ASM3P2474A
The ASM3P2474A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2474A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The ASM3P2474A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Product Description
The ASM3P2474A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2474A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of
all clock
dependent signals. The ASM3P2474A allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads and shielding that are
traditionally required to pass EMI regulations.
Key Specifications
Description
Supply voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency
Deviation
FSEL=0
FSEL=1
Specification
VDD = 3.3V
±
0.3V
200pS (Typ)
45/55% (worst case)
F
IN
/640
-1.5% (Typ) @ 50MHz
-1.5% (Typ) @ 25MHz
FSEL
Block Diagram
VDD
Modulation
XIN/CLKIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.

ASM3P2474A Related Products

ASM3P2474A ASM3P2474AF-08TT ASM3P2474AF-08ST ASM3P2474AG-08SR ASM3P2474AG-08ST ASM3P2474AG-08TT
Description Low Power Peak EMI Reducing Solution Low Power Peak EMI Reducing Solution Low Power Peak EMI Reducing Solution Low Power Peak EMI Reducing Solution Low Power Peak EMI Reducing Solution Low Power Peak EMI Reducing Solution
Maker - ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation]
Parts packaging code - SOIC SOIC SOIC SOIC SOIC
package instruction - TSSOP, SOP, SOP, SOP, TSSOP,
Contacts - 8 8 8 8 8
Reach Compliance Code - unknow unknow unknow unknow unknow
ECCN code - EAR99 EAR99 EAR99 EAR99 EAR99
JESD-30 code - R-PDSO-G8 R-PDSO-G8 R-PDSO-G8 R-PDSO-G8 R-PDSO-G8
length - 4.4 mm 4.9 mm 4.9 mm 4.9 mm 4.4 mm
Number of terminals - 8 8 8 8 8
Maximum operating temperature - 70 °C 70 °C 70 °C 70 °C 70 °C
Maximum output clock frequency - 60 MHz 60 MHz 60 MHz 60 MHz 60 MHz
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - TSSOP SOP SOP SOP TSSOP
Package shape - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Master clock/crystal nominal frequency - 30 MHz 30 MHz 30 MHz 30 MHz 30 MHz
Certification status - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height - 1.1 mm 1.75 mm 1.75 mm 1.75 mm 1.1 mm
Maximum supply voltage - 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage - 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount - YES YES YES YES YES
technology - CMOS CMOS CMOS CMOS CMOS
Temperature level - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form - GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch - 0.65 mm 1.27 mm 1.27 mm 1.27 mm 0.65 mm
Terminal location - DUAL DUAL DUAL DUAL DUAL
width - 3 mm 3.91 mm 3.91 mm 3.91 mm 3 mm
uPs/uCs/peripheral integrated circuit type - CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
Looking for project cooperation, outsourcing or graduation design related to DSP TMS320F2000 series or TMS320C6000 (DSP BIOS)
Looking for DSP TMS320F2000 or TMS320C6000 (6747/6713)/DSP BIOS related project cooperation or outsourcing, including audio, high-speed sampling, DSP bottom-level driver, etc. I am familiar with relat...
liang0125 Microcontroller MCU
How does Microblaze exchange data with external logic modules?
Can microblaze's GPIO exchange data with external logic modules? When I connect GPIO to external logic module in the top level file of ise, the following error occurs: ERROR:Xst:528 - Multi-source in ...
qd0090 FPGA/CPLD
How to insert gif in post?
I uploaded a gif in picture format, but in the end it seemed like only the first frame was available, with no animation effects. I've seen people post gifs in posts before....
johnrey Suggestions & Announcements
Let me show you the mini fan I got as a prize: See how I used it
I got it when I participated in the Intel data download. I was a little disappointed when I received it. It's for children, what can I do with it? There is no battery or anything like that. If I disas...
wangfuchong Talking
Why can't I crack Quartus II 9.0?
I followed the instructions on the Internet to crack it but couldn't crack it, why? For details, please see [url=http://zhidao.baidu.com/question/485218890.html?quesup2]http://zhidao.baidu.com/questio...
dayuruozhi0530 FPGA/CPLD
The company has a promising future and unlimited job potential. Talented people are welcome to join.
A technology company in Beijing is recruiting [ full-time or part-time]1. Responsible for the design of RF, microwave, and millimeter wave integrated circuit chips; 2. Responsible for the testing and ...
芯2022 Recruitment

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 355  1972  1644  35  1615  8  40  34  1  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号