Clock Synthesizer and Frequency Generator with Peak EMI reduction
Features
Dual PLL based Architecture
Operates with a 3.3V ±0.3V supply.
Generates an EMI optimized Spread Spectrum
PCI Clock output
Generates a high accuracy non Spread T1 clock of
±25ppm accuracy.
Generates a non spread system reference clock
Low power CMOS design.
Input frequency: 25 MHz.
Outputs:
Sys_ REF_CLK: 20 MHz
T1 Clock: 25 MHz (±25 ppm)
PCI_CLK: 33.33MHz Spread Spectrum
Frequency deviation: -0.5% (Typ).
Available in 8L SOIC Package.
The
ASM3P2508SP
uses
the
most
efficient
and
optimized modulation profile approved by the FCC.
ASM3P2508SP modulates the output of a PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in a significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’ (SSCG).
In
addition
to
the
SSCG
output,
ASM3P2508SP
generates two high accuracy clock signals -
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a
20MHz Sys_ REF_CLK.
Applications
The ASM3P2508SP is targeted towards Consumer,
Industrial, Data and Telecommunications applications.
Product Description
The ASM3P2508SP is a versatile Dual PLL based Clock
Synthesizer and Frequency Generator optimised and
designed specifically for three clock frequencies. The
PCI_CLK
output
from
ASM3P2508SP
reduces
Key Specifications
Description
Supply voltages
Input Frequency
Cycle-to-Cycle Jitter
Output Duty Cycle
Output Rise and Fall Time
SSC Modulation Rate
SSC Frequency Deviation
Specification
V
DD
= 3.3V ±0.3V
25 MHz
175 pS ( Max)
45/55%
1.1 nS (Max)
30KHz (Typ)
-0.5% (Typ)
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. ASM3P2508SP allows significant
system cost savings by reducing the number of circuit
board
layers,
ferrite
beads
&
shielding
that
are
traditionally required to pass EMI regulations.
Block Diagram
PWRDNB
V
DD
T1_CLK
Input
Divider
PLL 1
Output
Divider
Sys_REF_CLK
XIN/CLKIN
Osc
XOUT
PLL 2
Output
Divider
PCI_CLK
Modulation
V
SS
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
February 2005
rev 0.4
Pin Configuration
XIN/CLKIN
1
8
7
ASM3P2508SP
T1_CLK
V
SS
PCI_CLK
PWRDNB
XOUT
2
ASM3P2508SP
V
DD
3
Sys_REF_CLK
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
V
DD
Sys_REF_CLK
PWRDNB
PCI_CLK
V
SS
T1_CLK
Type
I
O
P
O
I
O
P
O
Description
Crystal connection or external reference frequency input. This pin has dual functions.
It can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Power supply for the entire chip
PLL 1 output System Reference Clock @ 20MHz
Power-down control pin. Pull low to enable power-down mode. Connect to V
DD
if not
used. Power -down Mode shuts off all the Outputs.
PLL 2 Spread spectrum clock output @ 33.33MHz
Ground to entire chip. Connect to system ground
Reference output T1 Clock @ 25MHz
Typical Modulation Profile
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD 22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
0 to 70
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
2 of 7
February 2005
rev 0.4
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
ASM3P2508SP
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Parameter
Min
V
SS
- 0.3
2.0
–
–
–
–
–
2.5
–
–
3.0
–
–
Typ
–
–
–
–
3
3
–
–
–
20
3.3
–
50
Max
0.8
V
DD
+ 0.3
-35
35
–
–
0.4
–
10
_
3.6
5
–
Unit
V
V
µA
µA
mA
mA
V
V
µA
mA
V
mS
Ω
XOUT output low current (@0.4V, V
DD
=3.3V)
XOUT output high current (@2.5V, V
DD
=3.3V)
Output low voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
Output high voltage (V
DD
= 3.3 V, I
OH
= 20 mA)
Static supply current *
Dynamic supply current
(3.3V, 33.33MHz, 25MHz , 20MHz and 15pF loading)
Operating voltage
Power-up time (first locked cycle after power up)**
Clock output impedance
* PWRDNB pin is pulled low
** V
DD
and XIN/CLKIN input are stable, PWRDNB pin is made high from low.
AC Electrical Characteristics
Symbol
XIN
PCI_CLK
T1_CLK
Sys_REF_CLK
PCI_CLK (SSCG)
t
LH
*
t
HL
*
t
JC
t
D
Modulation Rate
Deviation
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
Output frequency
Input frequency
Parameter
Min
–
–
24.999375
–
–
–
0.7
0.6
–
45
Typ
25
33.33
25
20
30
-0.5
0.9
0.8
150
50
Max
–
–
25.000625
–
–
–
1.0
1.0
175
55
Unit
MHz
MHz
MHz
KHz
%
nS
nS
pS
%
* t
LH
and t
HL
are measured into a capacitive load of 15pF
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
3 of 7
February 2005
rev 0.4
Typical Crystal Oscillator Circuit
ASM3P2508SP
Crystal
R1 = 510Ω
C1 = 27 pF
C2 = 27 pF
Typical Crystal Specifications
Fundamental AT cut parallel resonant crystal
Nominal frequency
Frequency tolerance
Operating temperature range
Storage temperature
Load capacitance
Shunt capacitance
ESR
25 MHz
± 25 ppm or better at 25°C
-25°C to +85°C
-40°C to +85°C
18pF
7pF maximum
25
Ω
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
4 of 7
February 2005
rev 0.4
Package Information
8-lead (150-mil) SOIC Package
ASM3P2508SP
E
H
D
A2
A
θ
e
B
A
1
C
L
D
Dimensions
Symbol
Min
A1
A
A2
B
C
D
E
e
H
L
θ
Inches
Max
0.010
0.069
0.059
0.020
0.010
0.004
0.053
0.049
0.012
0.007
Millimeters
Min
Max
0.10
1.35
1.25
0.31
0.18
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
0.41
0°
1.27
8°
0.25
1.75
1.50
0.51
0.25
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
0.016
0°
0.050
8°
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Notice: The information in this document is subject to change without notice.
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