LTC2217IUP-PBF datasheet, PDF - EEWORLD Datasheet

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LTC2217IUP-PBF: Description1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64; Categorysemiconductor logic; File Size1MB，32 Pages; ManufacturerLinear ( ADI ); Websitehttp://www.analog.com/cn/index.html

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LTC2217IUP-PBF Overview

1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64

LTC2217IUP-PBF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	3.3 V
Maximum linear error	0.0053 %
Maximum limit analog input voltage	2.75 V
Minimum limit analog input voltage	0.0 V
Processing package description	9 × 9 MM, plastic, MO-220WNJR, QFN-64
state	ACTIVE
packaging shape	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
surface mount	Yes
Terminal form	NO
Terminal spacing	0.5000 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
Sampling Rate	105 MHz
Output format	Parallel, WORD
Type of converter	proprietary method
Number of digits	16
Output bit encoding	OFFSET binary, 2S supplementary binary
Number of analog channels	1
Sample and hold and track and hold	SAMPLE

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LTC2217

16-Bit, 105Msps

Low Noise ADC

FEATURES

■

DESCRIPTION

The LTC

2217 is a 105Msps sampling 16-bit A/D converter

designed for digitizing high frequency, wide dynamic range

signals with input frequencies up to 400MHz. The input

range of the ADC is ﬁxed at 2.75V

P-P

The LTC2217 is perfect for demanding communications

applications, with AC performance that includes 81.3dBFS

Noise Floor and 100dB spurious free dynamic range

(SFDR). Ultra low jitter of 85fs

RMS

allows undersampling

of high input frequencies while maintaining excellent noise

performance. Maximum DC speciﬁcations include ±3.5LSB

INL, ±1LSB DNL (no missing codes).

The digital output can be either differential LVDS or

single-ended CMOS. There are two format options for the

CMOS outputs: a single bus running at the full data rate or

demultiplexed buses running at half data rate. A separate

output power supply allows the CMOS output swing to

range from 0.5V to 3.6V.

The ENC

and ENC

–

inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed with a wide range of

clock duty cycles.

Sample Rate: 105Msps

81.3dBFS Noise Floor

100dB SFDR

SFDR >90dB at 70MHz

85fs

RMS

Jitter

2.75V

P-P

Input Range

400MHz Full Power Bandwidth S/H

Optional Internal Dither

Optional Data Output Randomizer

LVDS or CMOS Outputs

Single 3.3V Supply

Power Dissipation: 1.19W

Clock Duty Cycle Stabilizer

Pin Compatible with LTC2208

64-Pin (9mm

9mm) QFN Package

APPLICATIONS

■

Telecommunications

Receivers

Cellular Base Stations

Spectrum Analysis

Imaging Systems

ATE

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Patents Pending.

TYPICAL APPLICATION

3.3V

SENSE

2.2μF

1.575V

COMMON MODE

BIAS VOLTAGE

INTERNAL ADC

REFERENCE

GENERATOR

0.5V TO 3.6V

1μF

CLKOUT

D15

•

OGND

CLOCK/DUTY

CYCLE

CONTROL

GND

ENC

–

SHDN

DITH

MODE

LVDS

RAND

1μF

3.3V

1μF

2217 TA01

64k Point FFT,

= 4.9MHz, –1dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

FREQUENCY (MHz)

2217 TA01b

ANALOG

INPUT

AIN

–

S/H

AMP

–

16-BIT

PIPELINED

ADC CORE

CORRECTION

LOGIC AND

SHIFT REGISTER

OUTPUT

DRIVERS

CMOS

LVDS

ADC CONTROL INPUTS

AMPLITUDE (dBFS)

AIN

2217f

LTC2217IUP-PBF Related Products

	LTC2217IUP-PBF	LTC2217CUP	LTC2217CUP-PBF	LTC2217CUP-TR	LTC2217CUP-TRPBF	LTC2217IUP	LTC2217IUP-TR	LTC2217IUP-TRPBF	LTC2217UP
Description	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64	1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	64	64	64	64	64	64	64	64	64
Maximum operating temperature	85 Cel	70 °C	85 Cel	85 Cel	85 Cel	85 °C	85 Cel	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-	-40 Cel	-40 Cel	-40 Cel	-40 °C	-40 Cel	-40 Cel	-40 Cel
surface mount	Yes	YES	Yes	Yes	Yes	YES	Yes	Yes	Yes
Terminal form	NO	NO LEAD	NO	NO	NO	NO LEAD	NO	NO	NO
Terminal location	Four	QUAD	Four	Four	Four	QUAD	Four	Four	Four
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Output format	Parallel, WORD	PARALLEL, WORD	Parallel, WORD	Parallel, WORD	Parallel, WORD	PARALLEL, WORD	Parallel, WORD	Parallel, WORD	Parallel, WORD
Number of digits	16	16	16	16	16	16	16	16	16
Rated supply voltage	3.3 V	-	3.3 V	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V
Maximum linear error	0.0053 %	-	0.0053 %	0.0053 %	0.0053 %	-	0.0053 %	0.0053 %	0.0053 %
Maximum limit analog input voltage	2.75 V	-	2.75 V	2.75 V	2.75 V	-	2.75 V	2.75 V	2.75 V
Minimum limit analog input voltage	0.0 V	-	0.0 V	0.0 V	0.0 V	-	0.0 V	0.0 V	0.0 V
Processing package description	9 × 9 MM, plastic, MO-220WNJR, QFN-64	-	9 × 9 MM, plastic, MO-220WNJR, QFN-64	9 × 9 MM, plastic, MO-220WNJR, QFN-64	9 × 9 MM, plastic, MO-220WNJR, QFN-64	-	9 × 9 MM, plastic, MO-220WNJR, QFN-64	9 × 9 MM, plastic, MO-220WNJR, QFN-64	9 × 9 MM, plastic, MO-220WNJR, QFN-64
state	ACTIVE	-	ACTIVE	ACTIVE	ACTIVE	-	ACTIVE	ACTIVE	ACTIVE
packaging shape	SQUARE	-	SQUARE	SQUARE	SQUARE	-	SQUARE	SQUARE	SQUARE
Package Size	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	-	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	Chip CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Terminal spacing	0.5000 mm	-	0.5000 mm	0.5000 mm	0.5000 mm	-	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	tin lead	-	tin lead	tin lead	tin lead	-	tin lead	tin lead	tin lead
Packaging Materials	Plastic/Epoxy	-	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy	-	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy
Sampling Rate	105 MHz	-	105 MHz	105 MHz	105 MHz	-	105 MHz	105 MHz	105 MHz
Type of converter	proprietary method	-	proprietary method	proprietary method	proprietary method	-	proprietary method	proprietary method	proprietary method
Output bit encoding	OFFSET binary, 2S supplementary binary	-	OFFSET binary, 2S supplementary binary	OFFSET binary, 2S supplementary binary	OFFSET binary, 2S supplementary binary	-	OFFSET binary, 2S supplementary binary	OFFSET binary, 2S supplementary binary	OFFSET binary, 2S supplementary binary
Number of analog channels	1	-	1	1	1	-	1	1	1
Sample and hold and track and hold	SAMPLE	-	SAMPLE	SAMPLE	SAMPLE	-	SAMPLE	SAMPLE	SAMPLE

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