ASM5P2304A-1-08-ST datasheet, PDF

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ASM5P2304A-1-08-ST: Description2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8; Categorylogic logic; File Size300KB，15 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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ASM5P2304A-1-08-ST Overview

2304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

ASM5P2304A-1-08-ST Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Reach Compliance Code	unknow
series	2304
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.008 A
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	4
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.2 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.91 mm
minfmax	133 MHz

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September 2005

rev 1.4

3.3V Zero Delay Buffer

Features

Zero input - output propagation delay, adjustable

by capacitive load on FBK input.

Multiple configurations - Refer “ASM5P2304A

Configurations Table”.

Input frequency range: 15MHz to 133MHz

Multiple low-skew outputs.

Output-output skew less than 200pS.

Device-device skew less than 500pS.

Two banks of four outputs.

Less than 200pS Cycle-to-Cycle jitter

(-1, -1H, -2, -2H).

Available in space saving, 8 pin 150-mil SOIC

packages.

3.3V operation.

Advanced 0.35< CMOS technology.

Industrial temperature available.

ASM5P2304A

the REF pin. The PLL feedback is required to be driven to

FBK pin, and can be obtained from one of the outputs. The

input-to-output propagation delay is guaranteed to be less

than 250pS, and the output-to-output skew is guaranteed to

be less than 200pS.

The ASM5P2304A has two banks of two outputs each.

Multiple ASM5P2304A devices can accept the same input

clock and distribute it. In this case the skew between the

outputs of the two devices is guaranteed to be less than

500pS.

The

ASM5P2304A

available

two

different

configurations (Refer “ASM5P2304A Configurations Table).

The ASM5P2304A-1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The ASM5P2304A-1H is the high-drive

version of the -1 and the rise and fall times on this device

are much faster.

The ASM5P2304A-2 allows the user to obtain REF and

1/2X or 2X frequencies on each output bank. The exact

configuration and output frequencies depend on which

output drives the feedback pin.

Functional Description

ASM5P2304A is a versatile, 3.3V zero-delay buffer

designed

distribute

high-speed

clocks

PC,

workstation, datacom, telecom and other high-performance

applications. It is available in 8 pin package. The part has

an on-chip PLL which locks to an input clock presented on

Block Diagram

FBK

CLKA1

REF

PLL

CLKA2

Extra Divider (-2)

CLKB1

CLKB2

Alliance Semiconductor

2575 Augustine Drive

•

Santa Clara, CA

•

Tel: 408.855.4900

•

Fax: 408.855.4999

•

www.alsc.com

Notice: The information in this document is subject to change without notice.

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