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CAT5401UI-25-TE13

Description
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface
CategoryAnalog mixed-signal IC    converter   
File Size98KB,17 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Download Datasheet Parametric View All

CAT5401UI-25-TE13 Overview

Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface

CAT5401UI-25-TE13 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCatalyst
Parts packaging codeTSSOP
package instructionLSSOP, TSSOP24,.25
Contacts24
Reach Compliance Codeunknow
ECCN codeEAR99
Other featuresNONVOLATILE MEMORY
control interface3-WIRE SERIAL
Converter typeDIGITAL POTENTIOMETER
JESD-30 codeR-PDSO-G24
JESD-609 codee0
length7.8 mm
Humidity sensitivity level1
Number of functions4
Number of positions64
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeLSSOP
Encapsulate equivalent codeTSSOP24,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)240
power supply3/5 V
Certification statusNot Qualified
resistance lawLINEAR
Maximum resistor tolerance20%
Maximum resistor terminal voltage3 V
Minimum resistor terminal voltage
Maximum seat height1.25 mm
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Nominal temperature coefficient300 ppm/°C
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Nominal total resistance2500 Ω
width4.4 mm
CAT5401
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
FEATURES
s
Four linear-taper digitally programmable
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Automatic recall of saved wiper settings at
potentiometers
s
64 resistor taps per potentiometer
s
End to end resistance 2.5k
, 10k
, 50k
or 100k
s
Potentiometer control and memory access via
power up
s
2.5 to 6.0 volt operation
s
Standby current less than 1
µ
A
s
1,000,000 nonvolatile WRITE cycles
s
100 year nonvolatile memory data retention
s
24-lead SOIC, 24-lead TSSOP and BGA
s
Industrial temperature range
SPI interface: Mode (0, 0) and (1, 1)
s
Low wiper resistance, typically 80Ω
s
Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of 63 resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper outputs
with CMOS switches. A separate 6-bit control register
(WCR) independently controls the wiper tap switches for
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (J, W)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
1
A
B
RW0
RL0
VCC
NC
RL3
RW3
NC
RL3
RH3
RW3
A0
SO
HOLD
SCK
RL2
RH2
RW2
NC
2
CS
WP
RH0
RH3
SO
A0
SI
A1
RL1
RH1
RW1
GND
NC
RW2
RH2
RL2
SCK
HOLD
3
A1
SI
RH1
RH2
HOLD
SCK
TSSOP Package (U, Y)
1
2
3
4
5
6
7
8
9
10
11
12
4
RL1
RW1
VSS
NC
RW2
RL2
24
23
22
21
20
CAT
19
5401
18
17
16
15
14
13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
RH0 RH1
RH2 R H3
CS
SCK
SI
SO
SPI BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R W0
R W1
R W2
WP
A0
A1
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R W3
RL0 RL1
RL2 R L3
BGA
C
D
E
F
Top View - Bump Side Down
Document No. 2010, Rev. F
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1

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