Xilinx® Defense-grade 7 series FPGAs comprise three FPGA families that address the complete range of system requirements, ranging from low cost,
small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the
high reliability requirements beyond commercial applications. The Defense-grade 7 series FPGAs include:
•
•
•
Artix®-7Q Family: Optimized for lowest cost and power with small form-factor packaging for the highest volume applications.
Kintex®-7Q Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.
Virtex®-7Q Family: Optimized for highest system performance and capacity with a 2X improvement in system performance.
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, Defense-grade 7 series FPGAs
enable an unparalleled increase in system performance with 1.4 Tb/s of I/O bandwidth, 980K logic cell capacity, and 4.7 TMAC/s DSP, while consuming
50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of Defense-Grade 7 Series FPGA Features
•
•
•
•
•
•
•
•
•
•
•
Full-range extended temperature testing
Mask set control
Fully leaded (Pb) content
Ruggedized packaging
Long-term availability
Anti-counterfeiting features
4th Generation Information Assurance and Anti-tamper support
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600 Mb/s to maximum rates of 6.6 Gb/s up to 11.3 Gb/s,
offering a special low-power mode, optimized for chip-to-chip
interfaces.
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•
•
•
•
•
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A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder
for high performance filtering, including optimized symmetric
in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS185 (v1.2) July 2, 2015
Product Specification
www.xilinx.com
1
Defense-Grade 7 Series FPGAs Overview
Artix-7Q FPGA Feature Summary
Table 2:
Artix-7Q FPGA Feature Summary by Device
Configurable Logic Blocks
(CLBs)
Device
Logic
Cells
Slices
(1)
8,150
15,850
33,650
Max
Distributed
RAM (Kb)
600
1,188
2,888
DSP48E1
Slices
(2)
18 Kb
120
240
740
150
270
730
36 Kb
75
135
365
Max (Kb)
2,700
4,860
13,140
5
6
10
1
1
1
4
4
8
Block RAM Blocks
(3)
CMTs
(4)
PCIe
(5)
GTPs
Analog
Mixed
Signal
(AMS)
1
1
1
Total I/O
Banks
(6)
Max
User
I/O
(7)
XQ7A50T
XQ7A100T
XQ7A200T
52,160
101,440
215,360
5
6
8
250
285
400
Notes:
1.
Each Defense-grade 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
2.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
4.
Each CMT contains one MMCM and one PLL.
5.
Artix-7Q FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
6.
Does not include configuration Bank 0.
7.
This number does not include GTP transceivers.
Table 3:
Artix-7Q FPGA Device-Package Combinations and Maximum I/Os
Package
Size (mm)
Ball Pitch (mm)
Device
XQ7A50T
XQ7A100T
XQ7A200T
0
210
4
285
GTP
CS324
15 x 15
0.8
I/O
HR
(2)
GTP
4
CS325
15 x 15
0.8
I/O
HR
(2)
150
GTP
RS484
19 x 19
0.8
I/O
HR
(2)
GTP
4
4
FG484
(1)
23 x 23
1.0
I/O
HR
(2)
250
285
4
285
8
400
GTP
RB484
(1)
23 x 23
1.0
I/O
HR
(2)
GTP
RB676
27 x 27
1.0
I/O
HR
(2)
Notes:
1.
Devices in FG484 and RB484 are footprint compatible
2.
HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.
DS185 (v1.2) July 2, 2015
Product Specification
www.xilinx.com
2
Defense-Grade 7 Series FPGAs Overview
Kintex-7Q FPGA Feature Summary
Table 4:
Kintex-7Q FPGA Feature Summary by Device
Device
Logic
Cells
Configurable Logic Blocks
(CLBs)
Slices
(1)
50,950
63,550
Max Distributed
RAM (Kb)
4,000
5,663
Block RAM Blocks
(3)
DSP
Slices
(2)
18 Kb
840
1,540
890
1,590
36 Kb
445
795
Max (Kb)
16,020
28,620
10
10
1
1
16
16
1
1
10
10
CMTs
(4)
PCIe
(5)
GTXs
XADC
Blocks
Total I/O
Banks
(6)
Max
User
I/O
(7)
500
500
XQ7K325T
XQ7K410T
326,080
406,720
Notes:
1.
Each Defense-grade 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
2.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
4.
Each CMT contains one MMCM and one PLL.
5.
Kintex-7Q FPGA Interface Blocks for PCI Express support up to x8 Gen 2.
6.
Does not include configuration Bank 0.
7.
This number does not include GTX transceivers.
Table 5:
Kintex-7Q FPGA Device-Package Combinations and Maximum I/Os
Package
Size (mm)
Ball Pitch (mm)
Device
XQ7K325T
XQ7K410T
GTX
8
8
RF676
27 x 27
1.0
I/O
HR
(1)
250
250
HP
(2)
150
150
GTX
16
16
RF900
31 x 31
1.0
I/O
HR
(1)
350
350
HP
(2)
150
150
Notes:
1.
HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.
2.
HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.
DS185 (v1.2) July 2, 2015
Product Specification
www.xilinx.com
3
Defense-Grade 7 Series FPGAs Overview
Virtex-7Q FPGA Feature Summary
Table 6:
Virtex-7Q FPGA Feature Summary
Device
Logic
Cells
Configurable Logic Blocks
(CLBs)
Slices
(1)
91,050
51,000
75,900
108,300
153,000
Max Distributed
RAM (Kb)
6,938
4,388
8,175
10,888
13,838
Block RAM Blocks
(3)
DSP
Slices
(2)
18 Kb
1,260
1,120
2,800
3,600
3,600
1,590
1,500
2,060
2,940
3,000
36 Kb
795
750
1,030
1,470
1,500
CMTs
Max
(Kb)
28,620
27,000
37,080
52,920
54,000
(4)
PCIe
(5)
GTX
GTH
GTZ
XADC
Blocks
Total I/O
Banks
(6)
Max
User
I/O
(7)
850
700
700
1,000
900
XQ7V585T
XQ7VX330T
XQ7VX485T
XQ7VX690T
XQ7VX980T
582,720
326,400
485,760
693,120
979,200
18
14
14
20
18
3
2
2
3
2
36
0
28
0
0
0
28
0
48
24
0
0
0
0
0
1
1
1
1
1
17
14
14
20
18
Notes:
1.
Each Defense-grade 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
2.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
4.
Each CMT contains one MMCM and one PLL.
5.
Virtex-7Q T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7Q XT Interface Blocks for PCI Express support up to x8 Gen 3, with the exception of
the XQ7VX485T device, which supports x8 Gen 2.
6.
Does not include configuration Bank 0.
7.
This number does not include GTX, GTH, or GTZ transceivers.
Table 7:
Virtex-7Q FPGA Device-Package Combinations and Maximum I/Os
Package
Size (mm)
Ball Pitch
Device
XQ7V585T
XQ7VX330T
XQ7VX485T
XQ7VX690T
XQ7VX980T
Notes:
1.
HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V.
2.
HP = High Performance I/O with support for I/O voltage from 1.2V to 1.8V.
0
20
0
600
0
48
0
350
GTX
20
0
RF1157
35 x 35
1.0
I/O
GTH
RF1158
35 x 35
1.0
I/O
HP
(2)
600
600
GTX
GTH
RF1761
42.5 x 42.5
1.0
I/O
HP
(2)
GTX
36
0
28
0
GTH
0
28
0
36
HR
(1)
100
50
0
0
HP
(2)
750
650
700
850
24
0
0
GTX
RF1930
45 x 45
1.0
I/O
GTH
HP
(1)
HR
(1)
0
0
HR
(1)
0
20
0
24
24
700
1,000
900
CLBs, Slices, and LUTs
Some key features of the CLB architecture include:
•
•
•
Real 6-input look-up tables (LUTs)
Memory capability within the LUT
Register and shift register functionality
The LUTs in Defense-grade 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or
as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can
optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry
logic form a slice, and two slices form a configurable logic block (CLB). Four of the eight flip-flops per slice (one per LUT) can
optionally be configured as latches.
Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two
SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.
DS185 (v1.2) July 2, 2015
Product Specification
www.xilinx.com
4
Defense-Grade 7 Series FPGAs Overview
Clock Management
Some of the key highlights of the clock management architecture include:
•
•
•
High-speed buffers and routing for low-skew clock distribution
Frequency synthesis and phase shifting
Low-jitter clock generation and jitter filtering
Each Defense-grade 7 series FPGA has up to 20 clock management tiles (CMTs), each consisting of one mixed-mode clock
manager (MMCM) and one phase-locked loop (PLL).
Mixed-Mode Clock Manager and Phase-Locked Loop
The MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies
and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which
speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).
There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration
and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency
comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because
it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen
appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°,
45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to
O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128.
The MMCM and PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth
mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but
not the best jitter attenuation. Optimized mode allows the tools to find the best setting.
MMCM Additional Programmable Features
The MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional
counters allow non-integer increments of
1
/
8
and can thus increase frequency synthesis capabilities by a factor of 8.
The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency.
Clock Distribution
Each Defense-grade 7 series FPGA provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and
the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and
extremely low skew.
Global Clock Lines
In each Defense-grade 7 series FPGA, 32 global clock lines have the highest fanout and can reach every flip-flop clock,
clock enable, and set/reset, as well as many logic inputs. There are 12 global clock lines within any clock region driven by
the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks to be turned off
within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven
by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are
often driven from the CMT, which can completely eliminate the basic clock distribution delay.
Regional Clocks
Regional clocks can drive all clock destinations in their region. A region is defined as any area that is 50 I/O and 50 CLB high
and half the chip wide. Defense-grade 7 series FPGAs have between six and twenty regions. There are four regional clock
tracks in every region. Each regional clock buffer can be driven from either of four clock-capable input pins, and its frequency
can optionally be divided by any integer from 1 to 8.
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