Data Sheet
FEATURES
18-Bit, 2 MSPS/1 MSPS/500 kSPS,
Precision, Pseudo Differential, SAR ADCs
AD4002/AD4006/AD4010
analog-to-digital converters (ADCs). The AD4002, AD4006,
and AD4010 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
respectively. They incorporate ease of use features that reduce
signal chain power consumption, reduce signal chain complexity,
and enable higher channel density. The high-Z mode, coupled with
a long acquisition phase, eliminates the need for a dedicated high
power, high speed ADC driver, thus broadening the range of
low power precision amplifiers that can drive these ADCs directly
while still achieving optimum performance. The input span com-
pression feature enables the ADC driver amplifier and the ADC
to operate off common supply rails without the need for a negative
supply while preserving the full ADC code range. The low serial
peripheral interface (SPI) clock rate requirement reduces the digital
input/output power consumption, broadens processor options,
and simplifies the task of sending data across digital isolation.
Operating from a 1.8 V supply, the AD4002/AD4006/AD4010
sample an analog input (IN+) from 0 V to V
REF
with respect to a
ground sense (IN−) with V
REF
ranging from 2.4 V to 5.1 V. The
AD4002 consumes only 14 mW at 2 MSPS with a minimum SCK
rate of 75 MHz in turbo mode; the AD4006 consumes only 7 mW
at 1 MSPS; and the AD4010 consumes only 3.5 mW at 500 kSPS.
The AD4002/AD4006/AD4010 all achieve ±3.2 LSB integral
nonlinearity error (INL) maximum, no missing codes at 18 bits,
and 95 dB signal-to-noise ratio (SNR) for an input frequency (f
IN
)
of 1 kHz. The reference voltage is applied externally and can be
set independently of the supply voltage.
The SPI-compatible versatile serial interface features seven different
modes including the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus, and provides an optional
busy indicator. The AD4002/AD4006/AD4010 are compatible
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
The AD4002/AD4006 are available in a 10-lead MSOP and
10-lead LFCSP, and the AD4010 is available in a 10-lead LFCSP,
with operation specified from −40°C to +125°C. The devices are
pin compatible with the 18-bit, 2 MSPS
AD4003
(see Table 8).
2.4V TO 5.1V
10µF
REF
V
REF
V
REF
/2
0
Throughput: 2 MSPS/1 MSPS/500 kSPS options
INL: ±3.2 LSB maximum
Guaranteed 18-bit, no missing codes
Low power: 70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
(VDD only)
SNR: 95 dB typical at 1 kHz, V
REF
= 5 V; 95 dB typical at 100 kHz
THD: −125 dB typical at 1 kHz, V
REF
= 5 V; −108 dB typical at
100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range
0 V to V
REF
with V
REF
from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay, valid first conversion
First conversion accurate
Guaranteed operation: −40°C to +125°C
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
Ability to daisy-chain multiple ADCs and busy indicator
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
GENERAL DESCRIPTION
The AD4002/AD4006/AD4010 are low noise, low power, high
speed, 18-bit, precision successive approximation register (SAR)
FUNCTIONAL BLOCK DIAGRAM
1.8V
VDD
TURBO
MODE
IN+
IN–
AD4002/
AD4006/
AD4010
HIGH-Z
MODE
18-BIT
SAR ADC
VIO 1.8V TO 5V
SDI
SCK
SDO
CNV
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
16233-001
SERIAL
INTERFACE
STATUS
BITS
CLAMP
SPAN
COMPRESSION
GND
Figure 1.
Rev. 0
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD4002/AD4006/AD4010
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Circuit Information .................................................................... 16
Converter Operation .................................................................. 17
Transfer Functions...................................................................... 17
Applications Information .............................................................. 18
Typical Application Diagrams .................................................. 18
Data Sheet
Analog Inputs.............................................................................. 19
Driver Amplifier Choice ........................................................... 20
Ease of Drive Features ............................................................... 21
Voltage Reference Input ............................................................ 23
Power Supply............................................................................... 23
Digital Interface .......................................................................... 24
Register Read/Write Functionality........................................... 24
Status Word ................................................................................. 27
CS Mode, 3-Wire Turbo Mode ................................................. 28
CS Mode, 3-Wire Without Busy Indicator ............................. 29
CS Mode, 3-Wire with Busy Indicator .................................... 30
CS Mode, 4-Wire Turbo Mode ................................................. 31
CS Mode, 4-Wire Without Busy Indicator ............................. 32
CS Mode, 4-Wire with Busy Indicator .................................... 33
Daisy-Chain Mode ..................................................................... 34
Layout Guidelines....................................................................... 35
Evaluating the AD4002/AD4006/AD4010 Performance ........ 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
1/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 37
Data Sheet
SPECIFICATIONS
AD4002/AD4006/AD4010
VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, V
REF
= 5 V, all specifications T
MIN
to T
MAX
, high-Z mode disabled, span compression disabled,
turbo mode enabled, and sampling frequency (f
S
) = 2 MSPS for the AD4002, f
S
= 1 MSPS for the AD4006, and f
S
= 500 kSPS for the AD4010,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Test Conditions/Comments
Min
18
0
−0.1
−0.1
0.1 × V
REF
0.3
1
Typ
Max
Unit
Bits
V
V
V
V
nA
µA
Analog Input Current
IN+ Voltage (V
IN+
) − IN− Voltage (V
IN−
)
V
IN+
to GND
V
IN−
to GND
Span compression enabled
Acquisition phase, T
A
= 25°C
High-Z mode enabled,
converting dc input at 2 MSPS
V
REF
V
REF
+ 0.1
+0.1
0.9 × V
REF
THROUGHPUT
Complete Cycle
AD4002
AD4006
AD4010
Conversion Time
Acquisition Phase
1
AD4002
AD4006
AD4010
Throughput Rate
2
AD4002
AD4006
AD4010
Transient Response
3
DC ACCURACY
No Missing Codes
Integral Nonlinearity Error (INL)
Differential Nonlinearity Error (DNL)
Transition Noise
Zero Error
Zero Error Drift
4
Gain Error
Gain Error Drift
4
Power Supply Sensitivity
1/f Noise
5
AC ACCURACY
Dynamic Range
Total RMS Noise
f
IN
= 1 kHz, −0.5 dBFS, V
REF
= 5 V
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion Ratio (SINAD)
Oversampled Dynamic Range
500
1000
2000
270
290
790
1790
0
0
0
290
320
ns
ns
ns
ns
ns
ns
ns
2
1
500
290
MSPS
MSPS
kSPS
ns
Bits
LSB
ppm
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
µV p-p
dB
µV rms
dB
dB
dB
dB
dB
18
−3.2
−12.2
−0.8
−18
−2.2
−45
−2.6
VDD = 1.8 V ± 5%
Bandwidth = 0.1 Hz to 10 Hz
±0.8
±3.1
±0.5
1.6
+3.2
+12.2
+0.8
+18
+2.2
+45
+2.6
±10
2
6
95.3
30.4
92.5
92
Oversampling ratio (OSR) = 256,
V
REF
= 5 V
Rev. 0 | Page 3 of 37
95
122
−125
95
119
AD4002/AD4006/AD4010
Parameter
f
IN
= 1 kHz, −0.5 dBFS, V
REF
= 2.5 V
SNR
SFDR
THD
SINAD
f
IN
= 100 kHz, −0.5 dBFS, V
REF
= 5 V
SNR
THD
SINAD
f
IN
= 400 kHz, −0.5 dBFS, V
REF
= 5 V
SNR
THD
SINAD
−3 dB Input Bandwidth
Aperture Delay
Aperture Jitter
REFERENCE
Voltage Range, V
REF
Current
AD4002
AD4006
AD4010
INPUT OVERVOLTAGE CLAMP
IN+/IN− Current, I
IN+
/I
IN−
V
IN+
/V
IN−
at Maximum I
IN+
/I
IN−
V
IN+
/V
IN−
Clamp On/Off Threshold
Deactivation Time
REF Current at Maximum I
IN+
DIGITAL INPUTS
Logic Levels
Input Low Voltage, V
IL
Input High Voltage, V
IH
Input Low Current, I
IL
Input High Current, I
IH
Input Pin Capacitance
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Output Low Voltage, V
OL
Output High Voltage, V
OH
I
SINK
= 500 µA
I
SOURCE
= −500 µA
Test Conditions/Comments
Min
87
Typ
89
122
−123.5
89
95
−108
94.8
94
−92
90
10
1
1
2.4
V
REF
= 5 V
2 MSPS
1 MSPS
500 kSPS
V
REF
= 5 V
V
REF
= 2.5 V
V
REF
= 5 V
V
REF
= 2.5 V
V
REF
= 5 V
V
REF
= 2.5 V
V
IN+
> V
REF
0.75
0.375
0.19
50
50
5.4
3.1
5.4
2.8
360
100
5.1
Max
Data Sheet
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
V
mA
mA
mA
mA
mA
V
V
V
V
ns
µA
87
5.25
2.68
VIO > 2.7 V
VIO ≤ 2.7 V
VIO > 2.7 V
VIO ≤ 2.7 V
−0.3
−0.3
0.7 × VIO
0.8 × VIO
−1
−1
6
+0.3 × VIO
+0.2 × VIO
VIO + 0.3
VIO + 0.3
+1
+1
V
V
V
V
µA
µA
pF
Serial 18 bits, straight binary
Conversion results available
immediately after completed
conversion
0.4
VIO − 0.3
V
V
Rev. 0 | Page 4 of 37
Data Sheet
Parameter
POWER SUPPLIES
VDD
VIO
Standby Current
Power Dissipation
Test Conditions/Comments
Min
1.71
1.71
VDD and VIO = 1.8 V, T
A
= 25°C
VDD = 1.8 V, VIO = 1.8 V, V
REF
= 5 V
10 kSPS, high-Z mode disabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
500 kSPS, high-Z mode enabled
1 MSPS, high-Z mode enabled
2 MSPS, high-Z mode enabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
500 kSPS, high-Z mode disabled
1 MSPS, high-Z mode disabled
2 MSPS, high-Z mode disabled
AD4002/AD4006/AD4010
Typ
1.8
1.6
70
3.5
7
14
3.8
7.6
15.2
2.5
4.9
9.75
0.95
1.9
3.65
0.1
0.2
0.6
7
−40
Max
1.89
5.5
Unit
V
V
µA
µW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
nJ/sample
°C
4.4
8.4
16.5
5.4
10.8
21.5
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE
Specified Performance
1
T
MIN
to T
MAX
+125
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the
AD4002, 1 MSPS for the AD4006, and 500 kSPS for the AD4010.
2
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3
Transient response is the time required for the ADC to acquire a full-scale input step to ±2 LSB accuracy. See Figure 39 for more information on ADC input settling for
multiplexed applications.
4
The minimum and maximum values are guaranteed by characterization, but not production tested.
5
See the 1/f noise plot in Figure 23.
Rev. 0 | Page 5 of 37
京公网安备 11010802033920号
EEWORLD
