IDT77301L12PF datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> storage> IDT77301L12PF

IDT77301L12PF: DescriptionFIFO, 128X9, 10ns, Synchronous, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size338KB，29 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric Compare View All

IDT77301L12PF Overview

FIFO, 128X9, 10ns, Synchronous, CMOS, PQFP100, TQFP-100

IDT77301L12PF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	_compli
ECCN code	EAR99
Maximum access time	10 ns
Maximum clock frequency (fCLK)	62 MHz
period time	16 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	1152 bi
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	128 words
character code	128
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128X9
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum slew rate	0.15 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm

IDT77301L12PF Preview

UTOPIA.I.O

1 TO 4

(128 X 9 X 4)

DEMULTIPLEXER-.I.O

.eatures:

♦

1,6%%!

General Description

The IDT77301 UtopiaFIFO is a high-speed, low power single input

port supplying four demultiplexing FIFO output ports. Each of the four

output synchronous (clocked) FIFOs are 64 words (128 bytes) in depth.

Data is written to the input port in “cells” (fixed length data packets). The

cell size is programmable from 16 bytes to 128 bytes.

The input port can be configured to support 9-bit or 18-bit wide data

buses. (Multiple 77301’s can be configured to handle 32 and 64-bit buses

with no additional logic.)

There are four routing methods that can be used to transfer data to the

77301. Two methods use out-band routing for the port selection, which

requires use of the Address Location bus. The remaining two methods

support in-band routing, which uses the Address Location bus in conjunc-

tion with the Data bus for port selection. Utopia 2 signaling supports single

cell transfers to single output ports, but the 77301 also offers a proprietary

multicasting protocol. Multicasting enables a single cell to be transferred

simultaneously to multiple selected output ports.

The four output ports can be configured as 9-bit or 4-bit wide data

buses. (18-bit wide buses can be supported with multiple 77301’s with no

Data transfers on fixed cell sizes

Programmable cell size

One input port to four output ports

Four Independent output 128 x 9 FIFO Queues

Selectable eighteen bit or nine bit input bus

Selectable eight/nine bit or four bit output buses

Programmable chip Identification

“UtopiaTx” level 2 compliant input interface signaling

“UtopiaTx” level 1 compliant output interface signaling

Separate clocks for input and output

Selectable In-band or Out-band routing

Multicast capability

Data clock rates to 62.5 MHz, 10ns access time

Building Block Implementation allows up to 32 output channels with

a 18, 36 or 64-bit input bus

Four 562 Mbps output channels can be derived from a single

1.1256 Gbps input channel with no additional glue logic

100-pin TQPF package

.unctional Block Diagram

128 BYTE

FIFO

RMS

MAS

BSS

ADR (0-4)

SOCR

SOCS - a

ENS

- a

CLAVS - a

Data - a (D0-D8)

SOCS - b

ENS

- b

CLAVS - b

Data - b (D0-D8)

SOCS - c

ENS

- c

CLAVS - c

Data - c (D0-D8)

SOCS - d

ENS

- d

CLAVS - d

Data - d (D0-D8)

128 BYTE

FIFO

ENR

CLAVR

Data (D0-D17)

WCLK

128 BYTE

FIFO

128 BYTE

FIFO

RST

MSE

BNE

CONTROL

RCLK

SLE

SCLK

SDI/P_ID0

3240 drw 01

MARCH 2001

DSC-3240/3

IDT77301

UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO

Commercial and Industrial Temperature Ranges

additional logic required.) Utopia 1 signalling protocol is supported for

these ports. Data can be read from each FIFO output port independently.

Separate input and output port clocks are provided and can be

operated up to 62.5 MHz. This provides the user with 1.125Gbps

composite bandwidth on the input port and 562Mbps bandwidth on each

output port.

Each 77301 has a unique programmable chip identification register.

Multiple UtopiaFIFOs with programmed chip identification can be utilized

to direct a 9, 18, 36 or 64-bit bus to as many as 31 output ports.

The principle application for the 77301 is in ATM networking based

systems, but can be used in any cell based data or telecommunications

application requiring the separation of independent data streams from a

single input channel.

.unctional Description

The signaling mode of operation is Utopia Transmit (UtopiaTx). With

UtopiaTx, data transfer is initiated by the device able to receive a cell by

asserting the TxCLAV (cell space available, CLAVR for the input port of

the 77301). The device sending data responds, if a cell is available for

transfer, by asserting the enable, TxENB (ENR and

ENS

for the 77301).

During the first byte transfer the TxSOC is asserted to identify the beginning

of the cell transfer. Successive clocks transfer the cell until the last data

transfer. The transfer can only be interrupted by the transmitting agent by

deasserting the TxENB signal. Once reasserted, the process will continue.

Upon completion of the last byte transfer, the condition for additional

transfers is determined by the TxCLAV and TxENB as before. This is

described in greater detail in the Utopia ATM-PHY Level 2 version 1

Document.

Pin Confituration

ENS

CLAVSa

GND

SOCSa

Data a 8

Data a 7

Data a 6

Data a 5

Vcc

Data a 4

Data a 3

Data a 2

Data a 1

Data a 0

GND

RCLK

SDI/P_ID0

SCLK

Data b 0

100

SLE

MSE

RMS

MAS

BNE

Data b 1

Data b 2

Vcc

Data b 3

Data b 4

Data b 5

Data b 6

Data b 7

GND

Data b 8

SOCSb

CLAVSb

ENS

Data c 0

Vcc

Data c 1

Data c 2

Data c 3

Data c 4

Data c 5

GND

Data c 6

Data c 7

Data c 8

SOCSc

77301

100 PIN

TQFP

PN-100

GND

BSS

ADR0

ADR1

ADR2

ADR3

ADR4

WCLK

DATA 0

Vcc

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Data 8

Data 9/P_ID0

GND

Data 10/P_ID1

Data 11/P_CS0

Data 12/P_CS1

Data 13/P_CS2

RST

CLAVR

GND

SOCR

Data17/P_CS6

Data16/P_CS5

Data15/P_CS4

Data14/P_CS3

CLAVSc

Vcc

ENS

Data d 0

Data d 1

Data d 2

Data d 3

GND

Data d 4

Data d 5

Data d 6

Data d 7

Data d 8

Vcc

SOCSd

CLAVSd

ENS

ENR

3 2 4 0 d rw 0 2

IDT77301

UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO

Commercial and Industrial Temperature Ranges

Pin Description

Symbol

1-2, 4-8,

10, 100

Name

DATA-b

I/O

Description

Data bus output for FIFO-b. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

Start Of Cell (FIFO-b). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts

for all remaining byte transfers.

Cell Available (FIFO-b). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.

Enable (FIFO-b). Master Mode:

ENS

is an active low output. When asserted, a data transfer will take

place on the current clock cycle. Slave Mode:

ENS

is an input which causes the fifo port to update a

data nibble (Q0-3) on the output bus on the next read clock edge.

Data bus output for FIFO-c. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus output is a data nibble (Q0-Q-3); Q4-Q6 data lines unused; data out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q1-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

Start Of Cell (FIFO-c). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts

for all remaining byte transfers.

Cell Available (FIFO-c) CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.

Enable (FIFO-c). Master Mode:

ENS

is an active low output. When asserted, a data transfer will take

place on the current clock cycle. Slave Mode:

ENS

is an input which causes the fifo port to update a

data nibble (Q0-3) on the output bus on the next read clock edge.

Data bus output for FIFO-d. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

high nibble transfer. Slave Mode with BNE LOW; data bus output is a data nibble (Q0-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

Start Of Cell (FIFO-d). Output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts

for all remaining byte transfers.

Cell Available (FIFO-d). CLAVS notifies the UtopiaFIFO port a cell transfer can be initiated by the port.

Enable (FIFO-d). Master Mode:

ENS

is an active low output. When asserted, a data transfer will take

place on the current clock cycle. Slave Mode:

ENS

is an input which causes the fifo port to update a

data nibble (Q0-3) on the output bus on the next read clock edge.

Input port write enable. Each data write requires

ENR

assertion.

Input port Cell space Available. Notifies the controlling agent the FIFO(s) selected by the address

bus can accept a complete cell.

Input port Start of Cell. Assertion: first work is currently on bus.

BSS low (18-Bit bus): Data bus input Data 11-Data 17

BSS high (9-bit bus): Input port for loading programmable registers.

3240 tbl 01

SOCS-b

CLAVS-b

I/O

ENS

-b

14, 16-20,

22-24

DATA-c

SOCS-c

CLAVS-c

I/O

ENS

-c

29-32,

34-38

DATA-d

SOCS-d

CLAVS-d

I/O

ENS

-d

47-53

ENR

CLAVR

SOCR

Data 17-11/

P_CS 6-0

IDT77301

UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO

Commercial and Industrial Temperature Ranges

Pin Description

Symbol

54, 56

57-64, 66

69-73

Name

Data 9-10 /

P_ID 0-1

Data 0-8

I/O

Description

18-Bit bus: Data bus input

9-bit bus: Parallel programmable register load (ID0, ID1)

Data bus input

Reset. Clears all FIFO memory locations, cell size read/write pointers.

Address Location(s). Provide cell destination and multicast addresses. Singlecast Operation: for out-

band routing, address location is loaded from incoming Utopia Level 2 compliant address lines; for

in-band routing, address location is derived from data lines D0-D17 (see Table 1a). Multicast

Operation for out-band routing, the ADR0-3 signals (ADR4 is not used) act as enables which select

the desired output FIFO combination (see Table 1b); for in-band routing, the output FIFO

co mbindation is derived from the data lines D0-D17.

Bus Size Select. BSS HIGH, the input bus is set to 9-bits (D0-D8) and D9-D17 determine cell size

and chip ID. BSS LOW, the input bus is 18-bits.

Input port Data write clock.

Byte Nibble Enable. BNE HIGH, output ports are byte wide data buses. BNE LOW, output data is in

4-bit "nibble" increments using Q0-Q3. This mode supports wide input data bus applications of 32 to

72-bit widths.

Multicast/Address Select. Determines single or multicast input mode. Selecting MAS HIGH sets the

device to multicast mode with ADR0-3 as enables. MAS LOW the device is set to single destination

mode with ADR0-4 lines as address lines.

Routing Method Select. With RMS HIGH, In-band Routing is selected. With RMS LOW, Out-band

Routing is selected.

Master Slave Enable. With MSE set HIGH, device is set as a master; with MSE LOW, device is set

as a slave.

Serial Load Enable.

Serial Load Clock.

BSS low, Serial data load. BSS high Serial input port for loading programmable registers.

Output Enable. Tri-States all data output buses.

Data read clock.

Data bus output for FIFO-a. Master Mode with BNE HIGH: output is a 9-bit word. Master Mode with

BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q6 data lines unused; data out Q7 is an

output enable control signal to the slave device; Q8 is an output of bit 9/18 valid during the low and

high nibble transfer. Slave Mode with BNE LOW: data bus output is a data nibble (Q0-Q3); Q4-Q7

lines unused; Q8 is an output of D8/D17 valid during the low and high nibble transfer.

Start Of Cell (FIFO-a) output from UtopiaFIFO. Active on first byte of data transfer. SOCS deasserts for

all remaining byte transfers.

Cell Available (FIFO-a). CLAVS notifies the UtopiaFIFO port. A cell transfer can be initiated by

the port.

Enable (FIFO-a). Master Mode:

ENS

is an active low output. When asserted, a data transfer will take

place on the current clock cycle. Slave Mode:

ENS

is an input which causes the fifo port to update a

data nibble (Q0-3) on the output bus on the next read clock edge.

Lo gic and supply ground pins 9, 21, 33, 45, 55, 75, 85 and 97.

Logic and supply V

pins 3, 15, 27, 39, 65, and 91.

3240 tbl 02

RST

ADR0-4

BSS

WCLK

BNE

MAS

86-90,

92-95

RMS

MSE

SLE

SCLK

SDI/P_ID0

RCLK

DATA-a

SOCS-1

CLAVS-a

I/O

ENS

-s

GND

____

IDT77301

UtopiaFIFO™ 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO

Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

Symbol

TERM

T-Bias

T-STG

OUT

Terminal Voltage with respect to ground

Operating Temperature

Temperature under Bias

Storage Temperature

DC Output Current

Rating

Commercial

-0.5 to +7.0

0 to +70

-55 to +155

Industrial

-0.5 to +7.0

-40 to +85

-55 to +155

Unit

3240 tbl 03

Recommended DC Operating Conditions

Symbol

GND

Commercial Supply Voltage

Supply Voltage

Input High Voltage Commercial

Input Low Voltage Commercial

Parameter

Min.

4.5

2.0

-0.3

Typ.

5.0

____

Max.

5.5

+0.3

0.8

Unit

3240 tbl 04

DC Electrical Characteristics

Symbol

CC1

Input Leakage Current

Output Leakage Current

Output Logic "1" Voltage, I

=-4mA@2.4V

Output Logic "0" Voltage I

=+4mA@0.4V

Input Low Voltage Commercial

Parameter

Min.

-1

-10

2.4

____

Typ.

____

Max.

____

Unit

µA

3240 tbl 05

____

0.4

150

____

Capacitance

Symbol

OUT

Input Capacitance

Output Capacitance

Parameter

Conditions

=0V

OUT

=0V

Max.

Unit

3240 tbl 06

Current

Symbol

-Active

-DC

Active Power Supply Current @ 20 MHz

DC Power Supply

Parameter

Conditions

Max.

Unit

3240 tbl 07

= High

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

IDT77301L12PF Related Products

	IDT77301L12PF	IDT77301L12PF8	IDT77301L12PF9	IDT77301L12PFI	IDT77301L12PFI8
Description	FIFO, 128X9, 10ns, Synchronous, CMOS, PQFP100, TQFP-100	FIFO, 128X9, 10ns, Synchronous, PQFP100, TQFP-100	FIFO, 128X9, 10ns, Synchronous, PQFP100, TQFP-100	FIFO, 128X9, 10ns, Synchronous, CMOS, PQFP100, TQFP-100	FIFO, 128X9, 10ns, Synchronous, PQFP100, TQFP-100
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFP	QFP	QFP	QFP	QFP
package instruction	TQFP-100	LFQFP,	LFQFP,	TQFP-100	LFQFP,
Contacts	100	100	100	100	100
Reach Compliance Code	_compli	unknown	unknown	_compli	unknow
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	10 ns	10 ns	10 ns	10 ns	10 ns
period time	16 ns	16 ns	16 ns	16 ns	16 ns
JESD-30 code	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e0	e0	e0	e0	e0
length	14 mm	14 mm	14 mm	14 mm	14 mm
memory density	1152 bi	1152 bit	1152 bit	1152 bi	1152 bi
memory width	9	9	9	9	9
Number of functions	1	1	1	1	1
Number of terminals	100	100	100	100	100
word count	128 words	128 words	128 words	128 words	128 words
character code	128	128	128	128	128
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	85 °C	85 °C
organize	128X9	128X9	128X9	128X9	128X9
Exportable	YES	YES	YES	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	TIN LEAD	TIN LEAD	Tin/Lead (Sn85Pb15)	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm	14 mm

Recommended Resources

LM108 bridge temperature measurement circuit

RC differential circuit

Tactile switch circuit diagram

Node timing switch circuit diagram

Compact Bridge Sense Amplifier Circuit

Double tube energy saving lamp circuit

Introduction to electromagnetic compatibility design methods (Part 5): After introducing several important concepts about electromagnetic radiation, we will introduce the methods and directions of countermeasure modification so that readers can not only understand some b...; taozi Power technology

Program for TMS570LS3137 development board: I bought a TMDS570LS31HDK, but does anyone have the sample program for this board? For example, a TF card....; feitian2017 Microcontroller MCU

How to design a frequency measurement circuit to measure the frequency of a crystal oscillator: The frequency of the crystal oscillator is 38KHz. How to design a frequency measurement circuit to measure the frequency of the crystal oscillator? Please explain it to me....; JERRR Analog electronics

C2000+Wenting 28335EVM+various materials: The laboratory bought Wenting 28335EVM a few years ago. 10 sets were used for teaching experiments, and the effect was pretty good~ It is said that when BOSS was in school, he wanted to learn DSP, but...; juring Microcontroller MCU

【KW41 Competition Work Submission】Wireless Data Acquisition System: Sorry, this project was delayed until the last minute due to various personal reasons. In fact, in my opinion, it only basically realizes the expected functions. If you want to achieve what can be cal...; sptt1 NXP MCU

I need help with questions about the topics TI has set for college e-sports competitions over the years.: Does anyone know where I can find the questions TI has given for the college electronic competitions over the years? Thanks...; 守月 Microcontroller MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components