M7A3PE1500-2FGG484 datasheet, PDF

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M7A3PE1500-2FGG484: DescriptionField Programmable Gate Array, 1500000 Gates, 38400-Cell, CMOS, PBGA484, 1 MM PITCH, GREEN, FBGA-484; CategoryProgrammable logic devices Programmable logic; File Size3MB，186 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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M7A3PE1500-2FGG484 Overview

Field Programmable Gate Array, 1500000 Gates, 38400-Cell, CMOS, PBGA484, 1 MM PITCH, GREEN, FBGA-484

M7A3PE1500-2FGG484 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	1 MM PITCH, GREEN, FBGA-484
Reach Compliance Code	compli
JESD-30 code	S-PBGA-B484
JESD-609 code	e1
length	23 mm
Humidity sensitivity level	3
Equivalent number of gates	1500000
Number of entries	280
Number of logical units	38400
Output times	280
Number of terminals	484
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1500000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA484,22X22,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	250
power supply	1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.44 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	23 mm

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v2.0

ProASIC

3E Flash Family FPGAs

with Optional Soft ARM

Support

Features and Benefits

High Capacity

•

600 k to 3 Million System Gates

108 to 504 kbits of True Dual-Port SRAM

Up to 616 User I/Os

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

Live at Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

1 kbit of FlashROM with Synchronous Interfacing

350 MHz System Performance

3.3 V, 66 MHz 64-Bit PCI

Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–

compliant)

FlashLock

to Secure FPGA Contents

Core Voltage for Low Power

Support for 1.5-V-Only Systems

Low-Impedance Flash Switches

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

Enhanced High-Speed, Very-Long-Line Network

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

•

700 Mbps DDR, LVDS-Capable I/Os

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X,

and

LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, BLVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V,

GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II,

SSTL3 Class I and II

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay

Schmitt Trigger Option on Single-Ended Inputs

Weak Pull-Up/Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages Across the ProASIC3E Family

Six CCC Blocks, Each with an Integrated PLL

Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback, Multiply/Divide,

Delay Capabilities, and External Feedback

Wide Input Frequency Range (1.5 MHz to 200 MHz)

CoreMP7Sd (with debug) and CoreMP7S (without debug

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,

×4, ×9, and ×18 Organizations Available)

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

CoreMP7Sd (with debug) and CoreMP7S (without

debug)

Reprogrammable Flash Technology

On-Chip User Nonvolatile Memory

High Performance

In-System Programming (ISP) and Security

Clock Conditioning Circuit (CCC) and PLL

Low Power

SRAMs and FIFOs

High-Performance Routing Hierarchy

Soft ARM7™ Core Support in M7 ProASIC3E Devices

•

Table 1 •

ProASIC3E Product Family

A3PE600

M7A3PE600

600 k

13,824

108

Yes

270

PQ208

FG256, FG484

A3PE1500

M7A3PE1500

1.5 M

38,400

270

Yes

444

PQ208

FG484, FG676

A3PE3000

M7A3PE3000

75,264

504

112

Yes

616

PQ208

FG484, FG896

ProASIC3E Devices

ARM-Enabled ProASIC3E Devices

System Gates

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

PQFP

FBGA

Notes:

Refer to the

CoreMP7

datasheet for more information.

The PQ208 package has six CCCs and two PLLs.

Six chip (main) and three quadrant global networks are available.

For devices supporting lower densities, refer to the

ProASIC3 Flash FPGAs

datasheet.

April 2007

See the Actel website for the latest version of the datasheet.

ProASIC3E Flash Family FPGAs

Table of Contents

Introduction and Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Device Architecture

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

Package Pin Assignments

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

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