AT17C002A-10JI datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > storage> storage> AT17C002A-10JI

AT17C002A-10JI: Description2M X 1 CONFIGURATION MEMORY, PQCC20; Categorystorage storage; File Size148KB，14 Pages; ManufacturerAtmel (Microchip)

Download Datasheet Parametric Compare View All

AT17C002A-10JI Overview

2M X 1 CONFIGURATION MEMORY, PQCC20

AT17C002A-10JI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	QLCC
package instruction	QCCJ, LDCC20,.4SQ
Contacts	20
Reach Compliance Code	unknow
ECCN code	EAR99
JESD-30 code	S-PQCC-J20
JESD-609 code	e0
length	8.9662 mm
memory density	2097152 bi
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Humidity sensitivity level	2
Number of functions	1
Number of terminals	20
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX1
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC20,.4SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum standby current	0.0005 A
Maximum slew rate	0.01 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8.9662 mm

Preview

Download Datasheet

View All

Features

•

Serial EEPROM Family for Configuring FLEX

Devices

•

Simple Interface to SRAM FPGAs

•

EE Programmable 2-Mbit Serial Memories Designed to Store Configuration Programs

•

for Field Programmable Gate Arrays (FPGAs)

Cascadable Read Back to Support Additional Configurations or Future Higher-density

Arrays

Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available in the Space-efficient Surface-mount PLCC Package

In-System Programmable via 2-wire Bus

Emulation of Atmel’s AT24CXXX Serial EEPROMs

Available in 3.3V ± 5% LV and 5V ± 5% C Versions

System-friendly READY Pin

Replacement for AT17C/LV002A

Description

The AT17C002A and AT17LV002A (high-density AT17A Series) FPGA Configuration

EEPROMs (configurators) provide an easy-to-use, cost-effective configuration mem-

ory for programming Altera FLEX devices. The AT17A Series is packaged in the

popular 20-lead PLCC and the 32-lead TQFP. The AT17A Series family uses a simple

serial-access procedure to configure one or more FPGA devices. The AT17A Series

organization supplies enough memory to configure one or multiple smaller FPGAs.

Using a feature of the AT17A Series, the user can select the polarity of the reset func-

tion by programming internal EEPROM bytes. The AT17A parts generate their own

internal clock and can be used as a system “master” for loading the FPGA devices.

The Atmel devices also support a system-friendly READY pin. The READY pin is used

to simplify system power-up considerations.

The AT17A Series Configurators can be programmed with industry-standard program-

mers or Atmel’s ATDH2200E Programming Kit.

FPGA

Configuration

EEPROM

Memory

2-megabit

Altera Pinout

AT17C002A

AT17LV002A

Rev. 2280B–08/01

AT17C/LV002A

Device

Configuration

The control signals for the configuration EEPROM (nCS, OE and DCLK) interface directly with

the FPGA device control signals. All FPGA devices can control the entire configuration pro-

cess and retrieve data from the configuration EEPROM without requiring an external intelligent

controller.

The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA output

pin and enable the address counter and the oscillator. When OE is driven Low, the configura-

tion EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also

controls the output of the AT17A Series Configurator. If nCS is held High after the OE reset

pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven Low,

the counter and the DATA output pin are enabled. When OE is driven Low again, the address

counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.

When the Configurator has driven out all of its data and nCASC is driven Low, the device tri-

states the DATA pin to avoid contention with other Configurators. Upon power-up, the address

counter is automatically reset.

The READY pin is available as an open-collector indicator of the device’s reset status; it is

driven Low while the device is in its power-on reset cycle and released (tri-stated) when the

cycle is complete.

This document discusses the EPF10K device interface. For more details or information on

other Altera applications, please reference the “AT17A Series Conversions from Altera FPGA

Serial Configuration Memories” application note.

FPGA Device

Configuration

FPGA devices can be configured with an AT17A Series EEPROM (see Figure 1). The AT17A

Series device stores configuration data in its EEPROM array and clocks the data out serially

with its internal oscillator. The OE, nCS and DCLK pins supply the control signals for the

address counter and the output tri-state buffer. The AT17A Series device sends a serial bit-

stream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the

FPGA device.

When the configuration data for an FPGA device exceeds the capacity of a single AT17A

Series device, multiple AT17A Series devices can be serially linked together (see Figure 2).

When multiple AT17A Series devices are required, the nCASC and nCS pins provide hand-

shaking between the cascaded EEPROMs.

The position of an AT17A Series device in a chain determines its operation. The first AT17A

Series device in a configurator chain is powered up or reset with nCS Low and is configured

for the FPGA device’s protocol. This AT17A Series device supplies all clock pulses to one or

more FPGA devices and to any downstream AT17A Series Configurator during configuration.

The first AT17A Series Configurator also provides the first stream of data to the FPGA devices

during multi-device configuration. Once the first AT17A Series device finishes sending config-

uration data, it drives its nCASC pin Low, which drives the nCS pin of the second AT17A

Series device Low. This activates the second AT17A Series device to send configuration data

to the FPGA device.

2280B–08/01

AT17C/LV002A

The READY pin is available as an open-collector indicator of the device’s reset status; it is

driven Low while the device is in its power-on reset cycle and released (tri-stated) when the

cycle is complete. It can be used to hold the FPGA device in reset while it is completing its

power-on reset but it cannot be used to effectively delay configuration (i.e., the output is

released well before the system V

has stabilized).

The first AT17A Series device clocks all subsequent AT17A Series devices until configuration

is complete. Once all configuration data is transferred and nCS on the first AT17A Series

device is driven High by CONF_DONE on the FPGA devices, the first AT17A Series device

clocks 16 additional cycles to initialize the FPGA device before going into zero-power (idle)

state. If nCS on the first AT17A Series device is driven High before all configuration data is

transferred – or if the nCS is not driven High after all configuration data is transferred – nSTA-

TUS is driven Low, indicating a configuration error.

AT17A Series

Reset Polarity

Programming

Mode

The AT17A Series Configurator allows the user to program the polarity of the OE pin as either

RESET/OE or RESET/OE. For more details, please reference the “Programming Specification

for Atmel’s FPGA Configuration EEPROMs” application note.

The programming mode is entered by bringing SER_EN Low. In this mode the chip can be

programmed by the 2-wire serial interface. The programming is done at V

supply only. Pro-

gramming supervoltages are generated inside the chip. See the “Programming Specification

for Atmel’s Configuration EEPROMs” application note for further information. The AT17 A-

series parts are read/write at 5V nominal. The AT17LV A-series parts are read/write at 3.3V

nominal.

The AT17A Series Configurator enters a low-power standby mode whenever nCS is asserted

High. In this mode, the configuration consumes less than 0.5 mA of current at 5V. The output

remains in a high-impedance state regardless of the state of the OE input.

Standby Mode

2280B–08/01

AT17C002A-10JI Related Products

	AT17C002A-10JI	AT17C002A	AT17LV020A	AT17C002A-10QC	AT17C002A-10QI	AT17C020A	AT17LV002A	AT17LV002A-10Q1
Description	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20	2M X 1 CONFIGURATION MEMORY, PQCC20
memory width	1	1	1	1	1	1	1	1
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	20	20	20	32	32	20	20	32
Maximum operating temperature	85 °C	85 Cel	85 Cel	70 °C	85 °C	85 Cel	85 Cel	85 °C
Minimum operating temperature	-40 °C	-40 Cel	-40 Cel	-	-40 °C	-40 Cel	-40 Cel	-40 °C
organize	2MX1	2M × 1	2M × 1	2MX1	2MX1	2M × 1	2M × 1	2MX1
surface mount	YES	Yes	Yes	YES	YES	Yes	Yes	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	J BEND	J BEND	J BEND	GULL WING	GULL WING	J BEND	J BEND	GULL WING
Terminal location	QUAD	Four	Four	QUAD	QUAD	Four	Four	QUAD

Recommended Resources

MC-1590 IF amplifier circuit diagram

Electric sewing machine power saving circuit

Exhaust fan automatic control circuit (1)

Simple automatic charger for NiCd batteries

12V regulated power supply circuit using photoelectric coupling as short circuit protection

LED signal amplifier circuit

Basic knowledge of LED backlight: [hide] 1. Technology of light source module: 　　The core technology of light source module is the optical technology of light guide plate. At present, there are mainly two types of light guide plates: ...; 探路者 LED Zone

Cable colors are subject to national standards and must be enforced. Did you know that: [b] In industrial and civil electricity, transmission cables must be marked with various colors. Are there any special regulations for these colorful cable colors? [/b] [b] Is it a mandatory requireme...; qwqwqw2088 Analogue and Mixed Signal

CC2430 and other TI series chips SPI communication program writing: This article introduces how to configure SPI for TI chips such as cc2430. The content is quite detailed~~...; 吸铁石上 RF/Wirelessly

Could you please tell me what is the function of the NL27WZ04 chip?: May I ask the experts what is the function of the NL27WZ04 chip? Does it have a plastic surgery function? Thank you...; wcht304 Analog electronics

Analog electronics learning: Uc is the control voltage. When Uc is high, the MOS tube is turned on when it is closed; when Uc is low, the MOS tube is turned off when it is open. Question: What are the functions of the diode, capa...; whwshiyuan1984 Analog electronics

NUCLEO Smart Home Gateway Solution Concept: Recently, I have been studying smart home and have been considering the implementation of home gateway. [size=3]There are two main solutions that I can think of. One is that the gateway builds its own...; 通宵敲代码 DIY/Open Source Hardware

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components