Features
•
Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
•
•
•
•
•
•
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera
®
FLEX
®
, APEX
™
Devices,
Lucent
®
ORCA
®
FPGAs, Xilinx
®
XC3000, XC4000, XC5200, Spartan
®
, Virtex
™
FPGAs,
Motorola
®
MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 5,000 Write Cycles Typical
LHF Package Available (Lead and Halide Free)
•
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•
•
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FPGA
Configuration
Flash Memory
AT17F040
AT17F080
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
44-lead PLCC and 44-lead TQFP, see
Table 1-1.
The AT17F Series Configurator
uses a simple serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package
8-lead LAP
20-lead PLCC
44-lead PLCC
44-lead TQFP
AT17F Series Packages
AT17F040
Yes
Yes
–
–
AT17F080
Yes
Yes
Yes
Yes
3039I–CNFG–2/05
3. Block Diagram
READY
Power-on
Reset
Reset
Clock/Oscillator
Logic
CLK
PAGE_EN
PAGESEL0
PAGESEL1
Config. Page
Select
CEO(A2)
Serial Download Logic
2-wire Serial Programming
DATA
Flash
Memory
CE/WE/OE
Data
Address
CE
Control Logic
RESET/OE
SER_EN
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
4
AT17F040/080
3039I–CNFG–2/05
AT17F040/080
5. Pin Description
Table 5-1.
Pin Description
AT17F040
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/
OE
CE
GND
CEO
A2
READY
SER_EN
V
CC
I/O
I/O
I
I
I
I
I
I
–
O
6
I
O
I
–
–
7
8
15
17
20
15
18
20
–
7
8
15
17
20
29
41
44
23
35
38
14
13
6
14
27
21
8
LAP
1
2
–
–
–
3
4
5
20
PLCC
2
4
16
11
7
6
8
10
20 PLCC
(Virtex)
1
3
–
–
–
8
10
11
8
LAP
1
2
–
–
–
3
4
5
AT17F080
20
PLCC
2
4
16
11
7
6
8
10
44
PLCC
2
5
1
20
25
19
21
24
44
TQFP
40
43
39
14
19
13
15
18
5.1
DATA
(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2
CLK
(1)
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5.3
PAGE_EN
(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 KΩ pull-up resistor.
2. This pin has an internal 30 KΩ pull-down resistor.
5
3039I–CNFG–2/05
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