3/4/6-Port DS3/E3 Integrated Line
Termination Device for ATM and Packet Processing
M29313/4/6 – DS3/E3 “Line-Card-on-a-Chip”
The M29313/4/6 provides a complete physical-layer solution
for flexible high-bandwidth clear channel and ATM DS3/E3
services. The M29313/4/6 replaces several discrete devices,
aggressively reducing cost, PCB real-estate and power
for DS3/E3 ports.
>
K E Y F E AT U R E S
>
High density – 3/4/6
DS3/E3 ports
>
High integration - LIUs with
DJAT, framers, ATM & HDLC
processors
>
Flexibility – mix ATM and
clear channel services
>
Easy implementation – TAP
software + high integration
= faster time-to-market
>
Pattern generators/
detectors for BERT
>
Comprehensive loopbacks
>
Minimal glue circuitry for line
and system interfacing
>
Supports DS3 C-parity, M13,
M23 & E3 G.832, G.751
>
Fractional DS3/E3 support
>
Embedded CLADs for
supported line rates
>
ATM/packet interfaces
- SPI-3 8-bit, 25–104 MHz for
ATM cells and HDLC packets
- UTOPIA Level 2 for
ATM/POS-PHY Level 2
for packets
Using the telecom application package (TAP) software
to abstract the physical registers, developers can easily
implement the M29313/4/6 solution, reducing design time.
The M29313/4/6 ‘line-card-on-a-chip’ includes 3/4/6 inde-
pendent DS3/E3 electrical line interface units (LIUs) with
built-in digital jitter attenuators (DJAT), and 3/4/6 DS3/E3
framers. The automatic line build out feature allows for
interfacing over 1800 feet of cable. The only requirement on
the line side is passive termination and transformers.
Each port operates independently and is supported by a
number of protocol options that may be selected from high
level data lnk controllers (HDLC) and ATM processors.
This flexibility allows service providers to provision both
ATM and clear channel DS3/E3 services on the same line
card. Fractional DS3/E3 service is also supported through
a bypass mode that allows external access to the DS3/E3
channel’s data stream between the framer and the
ATM/HDLC control allowing for external processing of the
payload. This mode also allows stacking of two M29316
devices to provide seamless support of 12 DS3/E3 line
side interfaces into one system side interface.
for ATM, and POS-PHY Level 2 for packets and/or SPI-3 for
ATM cells and HDLC packets.
The M29313/4/6 provides per channel integrated pattern
generators/detectors. A bit error rate test (BERT) can
be performed on any channel by means of the embedded
pattern generator/detector for pseudo-random bit
sequence (PRBS) or fixed 1 to 32-bit patterns for DS3/E3
framed/unframed operation. The M29313/4/6 also supports
a comprehensive set of loopbacks.
The M29313/4/6 requires only one 19.44 MHz reference
clock (passive crystal) for generating all the necessary
For flexibility, the M29313/4/6 incorporates independent
system interfaces to support cell and packet termination
into an industry-standard system bus of UTOPIA Level 2 (UL2)
internal line rate clocks and enabling the same reference
clock to be available.
The M29316/4/3 is offered in a 27 mm FCBGA package.
>
DS3/E3
Overhead
A ccess
Bypass/Chaining I/F
M29316
12x
AT M
Processors
UTOPIA L2
or
POS-PHY
L2
16-bit 50 MHz
ATM switch
or
IP router
Up to 6
DS3/
E3/
Lines
Lines
6x DS3/E3
LIU +JAT
6x
DS3/E3
Framers
12x
HDLC
Processors
SPI -3
(POS-PHY )
Interface
8-bit 104 MHz
ATM switch
or
IP router
6x PR BS
Generator
and Monitor
JTAG
Microprocessor Interface
MPC86 0
Test I/F
Systems Control
M29316 Functional Block Diagram
Product Features
• 3/4/6 DS3/E3 LIUs with DJAT
- Fully adaptive receive equalizer
enables greater than 1800 ft of cable
reach
- Fully programmable transmit pulse
mask configuration
• DS3/E3 framers support DS3-M13,
DS3-M23, DS3 C-bit parity E3-G.751,
E3-G.832
• 6/8/12 ATM processors support both
direct (for C-Bit parity or M23 DS3
and G.832 E3) and PLCP-based
mapping (for C-Bit parity M23, DS3
and E3-G.751)
• 6/8/12 bit-synchronous HDLC
processors
• ATM/packet interfaces
- SPI-3 8-bit 25–104 MHz for ATM cells
and HDLC packets
- UTOPIA Level 2 for ATM cells
/POS-PHY Level 2 for HDLC packets,
16-bit 25–50 MHz
• Fractional DS3/E3 interface for
external FPGA or ASIC
• Synchronous 16-bit microprocessor
interface bus at 30–77 MHz bus rate
- Glueless connection to Motorola
MPC860
• Local (source) and remote (line) loop-
back capability throughout internal
points in the device
• Embedded pattern generator/
detector for PRBS or fixed
1 to 32-bit sequence patterns
for framed/unframed modes
• JTAG (IEEE 1149.1) boundary scan
• Single rail 1.8 V core supply
with 3.3 V LvTTL I/O
• - 40C to +85C operation
• Embedded CLADs internally
generating the DS3/E3 line
rate clocks applications
• ATM switches
• ATM & IP DSLAM
• Edge routers
• BRAS/SMS platforms
• NGDLC
• MSPP
Ordering Information
• M29313-12P
• M29314-12P
• M29316-12P
www.mindspeed.com/salesoffices
General Information: (949) 579-3000
Headquarters – Newport Beach
4000 MacArthur Blvd., East Tower
Newport Beach, CA 92660-3007
29316-BRF-001-A M03-0787
© 2004 Mindspeed Technologies
™
. All rights reserved. Mindspeed and the Mindspeed
logo are trademarks of Mindspeed Technologies. All other trademarks are the property
of their respective owners. Although Mindspeed Technologies strives for accuracy in all
its publications, this material may contain errors or omissions and is subject to change
without notice.
This material is provided as is and without any express or implied
warranties, including merchantability, fitness for a particular purpose and non-
infringement.
Mindspeed Technologies shall not be liable for any special, indirect, inci-
dental or consequential damages as a result of its use.
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