MX28F160C3BT/B
16M-BIT [1M x16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Bit Organization: 1,048,576 x 16
• Single power supply operation
- VCC=VCCQ=2.7~3.6V for read, erase and program
operation
- VPP=12V for fast production programming
- Operating temperature:-40° C~85° C
• Fast access time : 70/90ns
• Low power consumption
- 9mA typical active read current, f=5MHz
- 18mA typical program current (VPP=1.65~3.6V)
- 21mA typical erase current (VPP=1.65~3.6V)
- 7uA typical standby current under power saving
mode
• Sector architecture
- Sector structure : 4Kword x 2 (boot sectors), 4Kword
x 6 (parameter sectors), 32Kword x 31 (main sectors)
- Top/Bottom Boot
• Auto Erase and Auto Program
- Automatically program and verify data at specified
address
- Auto sector erase at specified sector
• Automatic Suspend Enhance
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
• Automatic sector erase, word write and sector lock/
unlock configuration
• Status Reply
- Detection of program and erase operation comple-
tion.
- Command User Interface (CUI)
- Status Register (SR)
• Data Protection Performance
- Include boot sectors and parameter and main sectors
to be locked/unlocked
100,000 minimum erase/program cycles
Common Flash Interface (CFI)
128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User-Programmable
Latch-up protected to 100mA from -1V to VCC+1V
Package type:
- 48-pin TSOP (12mm x 20mm)
- 48-ball CSP (8mm x 6mm)
•
•
•
•
•
GENERAL DESCRIPTION
The MX28F160C3BT/B is a 16-mega bit Flash memory
organized as 1M words of 16 bits. The 1M word of data
is arranged in eight 4Kword boot and parameter sectors,
and thirty-one 32K word main sectors which are indi-
vidually erasable. MXIC's Flash memories offer the most
cost-effective and reliable read/write non-volatile random
access memory. The MX28F160C3BT/B is packaged in
48-pin TSOP and 48-ball CSP. It is designed to be re-
programmed and erased in system or in standard
EPROM programmers.
The standard MX28F160C3BT/B offers access time as
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX28F160C3BT/B uses a command register to man-
age this functionality. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
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MX28F160C3BT/B
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX28F160C3BT/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
A Command User Interface (CUI) serves as the inter-
face between the system processor and internal opera-
tion of the device. A valid command sequence written to
the CUI initiates device automation. An internal Write
State Machine (WSM) automatically executes the algo-
rithms and timings necessary for erase, word write and
sector lock/unlock configuration operations.
A sector erase operation erases one of the device's 32K-
word sectors typically within 1.0s, 4K-word sectors typi-
cally within 0.5s independent of other sectors. Each sec-
tor can be independently erased minimum 100,000 times.
Sector erase suspend mode allows system software to
suspend sector erase to read or write data from any other
sector.
Writing memory data is performed in word increments of
the device's 32K-word sectors typically within 0.8s and
4K-word sectors typically within 0.1s. Word program sus-
pend mode enables the system to read data or execute
code from any other memory array location.
MX28F160C3BT/B features with individual sectors lock-
ing by using a combination of bits thirty-nine sector lock-
bits and WP#, to lock and unlock sectors.
The status register indicates when the WSM's sector
erase, word program or lock configuration operation is
done.
The access time is 70/90/110ns (tELQV) over the oper-
ating temperature range (-40° C to +85° C) and VCC sup-
ply voltage range of 2.7V~3.6V.
MX28F160C3BT/B's power saving mode feature sub-
stantially reduces active current when the device is in
static mode (addresses not switching). In this mode, the
typical ICCS current is 7uA (CMOS) at 3.0V VCC.
As CE# and RESET# are at VCC, ICC CMOS standby
mode is enabled. When RESET# is at GND, the reset
mode is enabled which minimize power consumption and
provide data write protection.
A reset time (tPHQV) is required from RESET# switch-
ing high until outputs are valid. Similarly, the device has
a wake time (tPHEL) from RESET#-high until writes to
the CUI are recognized. With RESET# at GND, the WSM
is reset and the status register is cleared.
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MX28F160C3BT/B
BLOCK DIAGRAM
DQ0-DQ15
Output
Buffer
Input
Buffer
I/O
Logic
VCC
Output
Multiplexer
Identifier
Register
Data
Register
CE#
Command
User
Interface
WE#
OE#
RESET#
WP#
Status
Register
Data
Comparator
Write
State
Machine
A0~A19
Input
Buffer
Y
Decoder
Y-Gating
Program/Erase
Voltage Switch
VPP
VCC
GND
Main Sector 29
Boot Sector 0
Boot Sector 1
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
Parameter Sector
0
1
2
3
4
5
Main Sector 30
Main Sector 0
Main Sector 1
Address
Latch
X
Decoder
32K-Word
Main Sector
x31
.......
Address
Counter
.......
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MX28F160C3BT/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
Q15
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
MX28F160C3BT/B
48 Ball CSP (8mm x 6mm) Top View, Ball Down for MX28F160C3BT/BXA
(Ball Pitch=0.75mm, Ball Width=0.35mm)
A1
A13
B1
A14
C1
A15
D1
A16
E1
VCCQ
F1
GND
A2
A11
B2
A10
C2
A12
D2
DQ14
E2
DQ15
F2
DQ7
A3
A8
B3
WE#
C3
A9
D3
DQ5
E3
DQ6
F3
DQ13
A4
VPP
B4
RESET#
C4
NC
D4
DQ11
E4
DQ12
F4
DQ4
A5
WP#
B5
A18
C5
NC
D5
DQ2
E5
DQ3
F5
VCC
A6
A19
B6
A17
C6
A6
D6
DQ8
E6
DQ9
F6
DQ10
A7
A7
B7
A5
C7
A3
D7
CE#
E7
DQ0
F7
DQ1
A8
A4
B8
A2
C8
A1
6.0 mm
D8
A0
E8
GND
F8
OE#
8.0 mm
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MX28F160C3BT/B
Table 1. Pin Description
Symbol
A0-A19
Type
input
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Data inputs/outputs: Inputs array data on the second CE# and WE# cycle during a
program command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.
CE# high de-selects the memory device and reduce power consumption to standby
level. CE# is active low.
Reset/Deep Power Down: when RESET#=VIL, the device is in reset/deep power down
mode, which drives the outputs to High Z, resets the WSM and minimizes current level.
When RESET#=VIH, the device is normal operation. When RESET# transitions from
VIL to VIH, the device defaults to the read array mode.
WE#
VPP
input
input/supply
Write Enable: to control write to CUI and array sector. WE#=VIL becomes active. The
data and addresses are latched on the rising edge of the second WE# pulse.
Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V±5% for faster program and erase in a production environment.
Output enable: gates the device's outputs during a real cycle.
Write Protect: When WP# is VIL, the sectors marked Lock Down can't be unlocked
through software. When WP# is VIH, the lock down mechanism is disable and sectors
previously locked down are now locked and can be unlocked and locked through soft-
ware. After WP# goes low, any sectors previously marked lock down revert to that state.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers. (VCCQ must be tied to VCC)
Ground voltage: all the GND pin shall not be connected.
DQ0-DQ15
input/output
CE#
input
RESET#
input
OE#
WP#
input
input
VCC
VCCQ
GND
supply
input
supply
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