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AT22LV10-20PC

Description
OT PLD, 20ns, PAL-Type, CMOS, PDIP24
CategoryProgrammable logic devices    Programmable logic   
File Size410KB,12 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

AT22LV10-20PC Overview

OT PLD, 20ns, PAL-Type, CMOS, PDIP24

AT22LV10-20PC Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionDIP-24
Reach Compliance Codecompli
ArchitecturePAL-TYPE
maximum clock frequency41.6 MHz
JESD-30 codeR-PDIP-T24
length32 mm
Dedicated input times11
Number of I/O lines10
Number of entries22
Output times10
Number of product terms132
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
organize11 DEDICATED INPUTS, 10 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Programmable logic typeOT PLD
propagation delay20 ns
Maximum seat height5.08 mm
Maximum supply voltage5.5 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Features
Low-voltage Programmable Logic Device
– Wide Power Supply Range - 3.0V to 5.5V
– Ideal for Battery Powered Systems
High-speed Operation
– 20 ns Maximum Propagation Delay at V
CC
= 3.0V
Commercial and Industrial Temperature Ranges
Familiar 22V10 Logic Architecture
Low-power 3-volt CMOS Operation
AT22LV10L
Temp
I
CC
(mA)
Com./Ind.
4/5
AT22LV10
Com./Ind.
35/45
V
CC
= 3.6V
CMOS and TTL Compatible Inputs and Outputs
– 10 µA Leakage Maximum
Reprogrammable – Tested 100% for Programmability
High-reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
Dual-in-line and Surface Mount Packages
Low-voltage UV
Erasable
Programmable
Logic Device
AT22LV10
AT22LV10L
Logic Diagram
Description
The AT22LV10 and AT22LV10L are low-voltage compatible CMOS high-performance
Programmable Logic Devices (PLDs). Speeds down to 20 ns and power dissipation
as low as 14.4 mW are offered. All speed ranges are specified over the 3.0V to 5.5V
range. All pins offer a low
±
10 µA leakage.
The AT22LV10L provides the optimum low-power CMOS PLD solution, with low DC
power (1 mA typical at V
CC
= 3.3V) and full CMOS output levels. The AT22LV10L
significantly reduces total system power, allowing battery powered operation.
(continued)
Pin Configurations
Pin Name
CLK/IN
IN
I/O
*
VCC
Function
Clock and Logic Input
Logic Inputs
Bidirectional Buffers
No Internal Connection
3.0V to 5.5V Supply
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
CLK/IN
*
VCC
I/O
I/O
4
3
2
1
28
27
26
IN
IN
GND
*
IN
I/O
I/O
12
13
14
15
16
17
18
IN
IN
IN
*
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O
I/O
I/O
*
I/O
I/O
I/O
All Pinouts Top View
DIP/SOIC
PLCC
Rev. 0190E–08/99
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