DSC512-054213KI0T datasheet, PDF

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DSC512-054213KI0T: DescriptionOTHER CLOCK GENERATOR; CategoryThe embedded processor and controller Microcontrollers and processors; File Size672KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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DSC512-054213KI0T Overview

OTHER CLOCK GENERATOR

DSC512-054213KI0T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	HVQCCN,
Reach Compliance Code	compli
ECCN code	EAR99
Other features	CLK/CRYSTAL FREQ-NOM IS REPLACED WITH MEMS INTERNAL CLOCK
JESD-30 code	R-XQCC-N32
length	5 mm
Humidity sensitivity level	1
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	460 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Filter level	AEC-Q100
Maximum seat height	0.9 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	2.25 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	3.2 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

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DSC512-05

Crystal-less™ Four Output Clock Generator

General Description

The DSC512-05 is a Crystal-less™, four

output clock generator that implements

Discera’s

proven

PureSilicon™

MEMS

technology. The device provides excellent

jitter and stability over a wide range of

supply voltages and temperatures.

eliminating the external quartz crystal,

MEMS

clock

generators

significantly

enhance reliability and accelerate product

development, while meeting stringent clock

performance criteria for a variety of

communications, storage, and networking

applications.

DSC512-05 has an Output Enable / Disable

feature allowing it to disable all outputs

when OE1 and OE2 are low. Each output

enable pin controls one of the two banks of

synchronous clocks. See the OE function

table 1 for more detail.

The device is

available in a 20 pin QFN. Additional output

formats are in any combination of LVPECL,

LVDS, LVCMOS and HCSL.

Features



Two 50MHz (LVDS) Clocks



One 14MHz (LVCMOS) Clock



One 16MHz (LVCMOS) Clock



Available Format on Any Output:

HCSL, LVPECL, LVDS or LVCMOS

Ext. Industrial: -40° to 105° C

Industrial: -40° to 85° C

Ext. commercial: -20° to 70° C



Wide Temperature Range



Supply Range of 2.25 to 3.6 V



Low Power Consumption

30% lower than competing devices

Qualified to MIL-STD-883

20 QFN



Excellent Shock & Vibration Immunity



Available Footprints:



Lead Free & RoHS Compliant

Block Diagram*



Short Lead Time: 2 Weeks



AEC-Q100 Automotive Qualified



Applications



Communications/Networking



Embedded and Industrial



Consumer and computation



Medical, Military, Avionics



Storage and enterprise

In the above block diagram:

Clk0+ is 14MHz LVCMOS (Clk0- is off)

Clk1+/- and Clk2 +/- are 50MHz LVDS;

Clk3 + is 16MHz LVCMOS (Clk3- is off)

For other frequencies, please contact the factor:

Sales@discera.com

_____________________________________________________________________________________________________________________________ _________________

DSC512-05

Page 1

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