K7I323682M
K7I321882M
Document Title
1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Pin name change from DLL to Doff.
2. Vddq range change from 1.5V to 1.5V~1.8V.
3. Update JTAG test conditions.
4. Reserved pin for high density name change from NC to Vss/SA
5. Delete AC test condition about Clock Input timing Reference Level
6. Delete clock description on page 2 and add HSTL I/O comment
1. Update current characteristics in DC electrical characteristics
2. Change AC timing characteristics
3. Update JTAG instruction coding and diagrams
1. Add AC electrical characteristics.
2. Change AC timing characteristics.
3. Change DC electrical characteristics(ISB1)
1. Change the data Setup/Hold time.
2. Change the Access Time.(tCHQV, tCHQX, etc.)
3. Change the Clock Cycle Time.(MAX value of tKHKH)
4. Change the JTAG instruction coding.
1. Change the Boundary scan exit order.
2. Change the AC timing characteristics(-25, -20)
3. Correct the Overshoot and Undershoot timing diagrams.
1. Correct the JTAG ID register definition
2. Correct the AC timing parameter (delete the tKHKH Max value)
1. Change the Maximum Clock cycle time.
2. Correct the 165FBGA package ball size.
1. Change the operating current parameter.
before
after
Icc(x36) -25 :
620
700
-20 :
520
600
-16 :
440
500
Icc(x18) -25 :
560
670
-20 :
470
570
-16 :
410
470
Icc(x 8 ) -25 :
540
650
-20 :
450
550
-16 :
390
450
Isb1
-25 :
200
230
-20 :
180
200
-16 :
160
190
1. Final spec release
1. Delete the x8 Org. part
1. Change the operating current parameter
before
after
Isb1
-25 :
230
250
-20 :
200
230
-16 :
190
220
Draft Date
October, 22 2001
December, 12 2001
Remark
Advance
Preliminary
0.2
July, 29. 2002
Preliminary
0.3
Sep. 6. 2002
Preliminary
0.4
Oct. 7. 2002
Preliminary
0.5
Dec. 16, 2002
Preliminary
0.6
0.7
0.8
Mar. 20, 2003
April. 4, 2003
Oct. 29, 2003
Preliminary
Preliminary
Preliminary
1.0
2.0
2.1
Oct. 31, 2003
Dec. 1, 2003
July. 27, 2004
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
July. 2004
Rev 2.1
K7I323682M
K7I321882M
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
1Mx36-bit, 2Mx18-bit DDRII CIO b2 SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
freguency scaling.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Pipelined, double-data rate operation.
• Common data input/output bus .
• HSTL I/O
• Full data coherency, providing most current data.
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two input clocks for output data(C and C) to minimize
clock-skew and flight-time mismatches.
• Two echo clocks (CQ and CQ) to enhance output data
traceability.
• Single address bus.
• Byte write (x18, x36) function.
• Simple depth expansion with no data contention.
• Programmable output impedance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
Organization
Part
Number
K7I323682M-FC25
X36
K7I323682M-FC20
K7I323682M-FC16
K7I321882M-FC25
X18
K7I321882M-FC20
K7I321882M-FC16
Cycle
Time
4.0
5.0
6.0
4.0
5.0
6.0
Access
Unit
Time
0.45
0.45
0.50
0.45
0.45
0.50
ns
ns
ns
ns
ns
ns
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
DATA
REG
36 (or 18)
19
(or 20)
WRITE/READ DECODE
WRITE DRIVER
OUTPUT SELECT
LD
R/W
BW
X
4(or 2)
CTRL
LOGIC
1Mx36
(2Mx18)
MEMORY
ARRAY
36
(or 18)
72
(or 36)
OUTPUT DRIVER
ADDRESS
A0
SENSE AMPS
OUTPUT REG
19 (or 20)
ADD REG
&
BURST
LOGIC
36 (or 18)
DQ
CQ, CQ
K
K
C
C
(Echo Clock out)
CLK
GEN
SELECT OUTPUT CONTROL
Notes:
1. Numbers in ( ) are for x18 device
DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.
-2-
July. 2004
Rev 2.1
K7I323682M
K7I321882M
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA*
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW
1
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS/
SA*
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7I323682M(1Mx36)
Notes :
1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 10A for 72Mb, 2A for 144Mb .
2. BW
0
controls write to DQ0:DQ8, BW
1
controls write to DQ9:DQ17, BW
2
controls write to DQ18:DQ26 and BW
3
controls write to DQ27:DQ35.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA0
SA
DQ0-35
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
4A
8A
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
10R
11R
2R
1R
1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
1
NOTE
R/W
LD
BW
0
, BW
1,
BW
2
, BW
3
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-3-
July. 2004
Rev 2.1
K7I323682M
K7I321882M
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA*
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
PIN CONFIGURATIONS
(TOP VIEW)
K7I321882M(2Mx18)
Notes:
1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 2A for 72Mb.
2. BW
0
controls write to DQ0:DQ8 and BW
1
controls write to DQ9:DQ17.
PIN NAME
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA0
SA
DQ0-17
R/W
LD
BW
0
, BW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C
3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
Data Inputs Outputs
Read, Write Control Pin, Read active
when high
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply ( 1.5V or 1.8V )
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
1
NOTE
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
July. 2004
Rev 2.1
K7I323682M
K7I321882M
GENERAL DESCRIPTION
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
The K7I323682M and K7I321882M are 37,748,736-bits DDR Common I/O
Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for K7I323682M and 2,097,152 words by 18 bits for K7I321882M .
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read data are referenced to echo clock ( CQ or CQ ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW
0
and BW
1
( BW
2
and BW
3)
pins for x18 ( x36 ) device.
Nybble write operation is supported with NW
0
and NW
1
pins for x8 device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7I323682M and K7I321882M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit, 18-bit or 8-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K insted of C and C.
When the LD is disabled after a read operation, the K7I323682M and K7I321882M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Echo clock operation
To assure the output tracibility, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transfered to external through same structures
as output driver.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
-5-
July. 2004
Rev 2.1
京公网安备 11010802033920号
EEWORLD
