VP16256
Programmable FIR FIlter
Advance Information
DS4548
ISSUE 4.0
August 1998
The VP16256 contains sixteen multiplier - accumulators, which
can be multi cycled to provide from 16 to 128 stages of digital filtering.
Input data and coefficients are both represented by 16-bit two’s
complement numbers with coefficients converted internally to 12 bits
and the results being accumulated up to 32 bits.
In 16-tap mode the device samples data at the system clock rate
of up to 40MHz. If a lower sample rate is acceptable then the number
of stages can be increased in powers of two up to a maximum of 128.
Each time the number of stages is doubled, the sample clock rate
must be halved with respect to the system clock. With 128 stages the
sample clock is therefore one eighth of the system clock.
In all speed modes devices can be cascaded to provide filters of
any length, only limited by the possibility of accumulator overflow. The
32-bit results are passed between cascaded devices without any
intermediate scaling and subsequent loss of precision.
The device can be configured as either one long filter or two
separate filters with half the number of taps in each. Both networks
can have independent inputs and outputs.
Both single and cascaded devices can be operated in decimate-
by-two mode. The output rate is then half the input rate, but twice the
number of stages are possible at a given sample rate. A single device
with a 40MHz clock would then, for example, provide a 128-stage low
pass filter, with a 10MHz input rate and 5MHz output rate.
Coefficients are stored internally and can be down loaded from
a host system or an EPROM. The latter requires no additional
support, and is used in stand alone applications. A full set of
coefficients is then automatically loaded at power on, or at the request
of the system. A single EPROM can be used to provide coefficients
for up to 16 devices.
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
RES
PIN 1
PIN 1 IDENT
PIN
208
GH208
Pin identification diagram (top view)
See Table 1 for pin descriptions and Table 2 for pinout
INPUT
DATA
VP
16256
EPROM
SCLK
GND
OUTPUT
DATA
Fig. 1 A dual filter application
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
RES
COEFFICIENTS
FEATURES
I
Sixteen MACs in a Single Device
I
Basic Mode is 16-Tap Filter at up to 40MHz
Sample Rates
I
Programmable to give up to 128 Taps with
Sampling Rates Proportionally Reducing to 5MHz
I
16-bit Data and 32-bit Accumulators
I
Can be configured as One Long Filter or Two Half-
Length Filters
I
Decimate-by-two Option will Double the Filter
Length
I
Coefficients supplied from a Host System or a local
EPROM
I
208-Pin Plastic PowerQuad PQ2 Package
APPLICATIONS
I
High Performance Commercial Digital Filters
I
Matrix Multiplication
I
Correlation
I
High Performance Adaptive Filtering
VP
16256
ANALOG
INPUT
ADC
EPROM
CLKOP
SCLK
GND
OUTPUT
DATA
ORDERING INFORMATION
VP16256-27/CG/GH1N
27MHz, Commercial
PowerQuad PQ2 package (GH208)
VP16256-40/CG/GH1N
40MHz, Commercial
PowerQuad PQ2 package (GH208)
plastic
plastic
Fig. 2 Typical system application
VP16256
Signal
DA15:0
DB15:0
X31:0
16-bit data input bus to Network A.
Delayed data output bus in the single filter mode. Connected to the data input bus of the next device in a
cascaded chain. Input to Network B in the dual filter modes.
Expansion input bus in the single filter mode. Connected to the previous filter output in a cascaded chain.
The inputs are not used on a single device system or on the Termination device in a cascaded chain. The
X bus provides the output from Network B in both dual modes.
In single filter mode this bus holds the main device output. In dual mode it holds the output from Network A.
Filter enable. The first high present on an SCLK rising edge defines the first data sample. The control
register and coefficient memory must be configured before FEN is enabled. The signal must stay active
whilst valid data is being received and must be low if FRUN is high.
Delayed filter enable. This output is connected to the Filter Enable input of the next device in a cascaded
chain when moving towards the termination device and with multiple stand-alone EPROM-loaded
configurations. It is used to coordinate the control logic within each device.
Selects either the upper or lower set of coefficients for Bank Swap. A low selects the lower bank, a high
the upper bank.
In EPROM load mode, when high this signal allows continuous filter operations to occur without the need for
the initial FEN edge. If the device is not a single, interface or master device then this pin must be tied low.
A low on this signal on the SCLK rising edge will clear all the internal accumulators. DCLR need only remain
low for a single cycle, signal BUSY will indicate when the internal clearing is complete. After a clear the
device must be re-synchronised to the data stream using FEN. It is recommended that FEN is taken low
at the same time as clear. FEN may then be taken high to synchronise the data stream once BUSY has
returned low.
16-bit coefficient input bus. In the Byte mode of operation, C15:8 have alternative uses as explained in the
text.
Coefficient address bus. In the EPROM mode A7:0 are address outputs for an EPROM. In the remote host
mode they are inputs from the host. A7 is not used when coefficients are loaded as 16-bit words.
This pin is similar in operation to A7:0 and provides a higher order address bit. When low the coefficients
are loaded, when high the control register is loaded.
In the remote mode this pin is an input which when low enables the load operation. In the EPROM mode
it is an output which provides the write enable for other slave devices.
This pin is always an input and must also be low for the internal write operation to occur.
When this pin is tied low, coefficients are loaded as two 8-bit bytes. When the pin is high they are loaded
as 16-bit words. In the EPROM mode this pin is ignored.
When this pin is tied low coefficients are loaded as bytes from an external EPROM. The device outputs
an address on A7:0. When the pin is high coefficients must be loaded from a remote master. They can then
be transferred individually rather than as a complete set.
The main system clock; all operations are synchronous with this clock. The clock rate must be either 1, 2,
4, or 8 times the required data sampling rate. The factor used depends on the required filter length.
This output, when used to enable SCLK, can provide a data sampling clock. It has the effect of dividing
the SCLK rate by 1, 2, 4 or 8 depending on the filter mode selected.
Tri-state enable for the F bus. When high the outputs will be high impedance. OEN is registered onto the
device and does not therefore take effect until the first SCLK rising edge
A high on this signal indicates that the device is completing internal operations and is not yet able to accept
new data. The signal is used during automatic EPROM loading, reset and accumulator clearing.
When this pin is low the control logic and accumulators are reset. In the EPROM mode it will initiate a load
sequence when it goes high.
Description
F31:0
FEN
DFEN
SWAP
FRUN
DCLR
C15:0
A7:0
CCS
WEN
CS
BYTE
EPROM
SCLK
CLKOP
OEN
BUSY
RES
NOTES
1. Unused buses (e.g. X31:0 when the device is configured in single or termination mode) can be set to any value. They should however be
maintained at a valid logic level to avoid an increase in power consumption.
2. To ensure correct input voltage thresholds are maintained all the V
DD
and GND pins must be connected to adequate power and ground planes.
Table 1 Pin descriptions
2
VP16256
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Signal
V
DD
F0
F1
GND
F2
F3
V
DD
F4
F5
GND
F6
F7
V
DD
F8
GND
F9
F10
V
DD
F11
F12
GND
F13
F14
F15
V
DD
F16
F17
GND
F18
F19
V
DD
F20
F21
F22
F23
V
DD
F24
F25
GND
F26
V
DD
F27
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Signal
F28
F29
GND
F30
F31
V
DD
FEN
DFEN
DCLR
GND
SWAP
GND
OEN
CLKOP
V
DD
DA0
V
DD
DA1
GND
DA2
V
DD
DA3
DA4
V
DD
DA5
GND
DA6
DA7
DA8
DA9
V
DD
DA10
GND
DA11
DA12
DA13
DA14
V
DD
DA15
GND
C0
C1
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Signal
GND
C2
V
DD
C3
C4
C5
C6
V
DD
C7
GND
C8
C9
C10
GND
C11
C12
C13
V
DD
C14
V
DD
C15
GND
GND
WEN
CCS
CS
V
DD
RES
GND
SCLK
GND
V
DD
BYTE
EPROM
A0
V
DD
A1
GND
A2
A3
A4
V
DD
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Signal
A5
A6
GND
A7
DB0
V
DD
DB1
GND
DB2
DB3
DB4
V
DD
DB5
GND
DB6
DB7
V
DD
DB8
V
DD
DB9
DB10
GND
DB11
DB12
V
DD
DB13
DB14
GND
DB15
V
DD
GND
BUSY
X0
V
DD
X1
GND
X2
V
DD
X3
X4
X5
X6
Pin
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Signal
GND
X7
X8
V
DD
X9
GND
X10
X11
X12
V
DD
X13
X14
GND
X15
X16
X17
V
DD
X18
GND
X19
X20
X21
V
DD
X22
GND
X23
X24
X25
X26
GND
X27
V
DD
X28
X29
X30
GND
X31
V
DD
FRUN
GND
Table 2 VP16256 pinout (208-pin Power PQFP - GH208)
3
VP16256
DA15:0
F31:0
OEN
SCLK
FRUN
SWAP
A7:0
C15:0
CCS
WEN
CS
BYTE
EPROM
FEN
DFEN
DCLR
RES
NETWORK
A
COEFFICIENT
STORAGE
AND
CONTROL
DUAL
MODE
MUX
NETWORK
B
SINGLE
MODE
CLKOP
BUSY
DB15:0
X31:0
Fig. 3 Block Diagram
OPERATIONAL OVERVIEW
The VP16256 is an application specific FIR filter for use in
high performance digital signal processing systems. Sampling
rates can be up to 40MHz. The device provides the filter
function without any software development, and the options
are simply selected by loading a control register. The device
can be user configured as either a single filter, or as two
separate filters. The latter can provide two independent filters
for the in-phase and quadrature channels after IQ splitting, or
can provide two filters in cascade for greater stop band
rejection.
The device operates from a system clock, with rates up to
40MHz. This clock must be 1, 2, 4, or 8 times the required
sampling frequency, with the higher multiplication rates
producing longer filter networks at the expense of lower
sampling rates. Devices can be connected in cascade to
produce longer filter lengths. This can be accomplished
without the need for any additional external data delays, and all
the single device options remain available.
Continuous inputs are accepted, and continuous results
produced after the internal pipeline delay. Connection can be
made directly to an A-D converter. The filter operation can be
synchronised to a Filter Enable signal (FEN) whose positive
going edge marks the first data sample. The internal multiplier
accumulator array can be cleared with a dedicated input. This
is necessary if erroneous results obtained during the normal
data ‘flush through’ are not permissible in the system.
Coefficients can be loaded from a host system using a
conventional peripheral interface and separate data bus.
Alternatively, they can be loaded as a complete set from a byte
wide EPROM. The device produces addresses for the EPROM
and a BUSY output indicates that the transfer is occurring. Up
to sixteen devices can have their coefficients supplied from a
single EPROM. These devices need not necessarily be part of
the same filter network.
Each of the filter networks shown in Fig. 3 contains eight
systolic multiplier accumulator stages; an example with four
stages is shown in Fig. 4. Input data flows through the delay
lines and is presented for multiplication with the required
coefficient. This is added to either the last result from this
accumulator or the result from the previous accumulator. The
filter results progress along the adders at the data sample rate.
If the sample rate equals SCLK divided by four, for example,
then the accumulated result is passed onto the next stage
every fourth cycle. The structure described is highly efficient
when used to calculate filtered results from continuous input
data.
A comprehensive digital filter design program is available
for PC compatible machines. This will optimise the filter
coefficients for the filter type required and number of taps
available at the selected sample rate within the VP16256
device. An EPROM file can be automatically generated in
Motorola S-record format.
4
VP16256
DATA
OUT
DATA
IN
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
DATA
DELAY LINE
COEFF
RAM
ACCUMULATE
EXPANSION
IN
COEFF
RAM
COEFF
RAM
COEFF
RAM
RESULT
OUT
ADDER
ADDER
ADDER
ADDER
Z
2
1
Z
2
1
Z
2
1
Z
2
1
Fig. 4 Filter network diagram
SINGLE FILTER OPTIONS
When operating as a single filter the device accepts data on
the 16-bit DA bus at the selected sample rate, see Figs. 5 and 6.
Results are presented on the 32-bit F bus, which may be
tristated using the OEN input. Signal OEN is registered onto the
device and does not therefore take effect until the first SCLK
rising edge. Devices may be cascaded this allows filters with
more taps than available from a single device. To accomplish
this two further buses are utilised. The DB bus presents the
input data to the next device in cascade after the appropriate
delay, while, partial results are accepted on the
X bus.
Single filter mode is selected by setting control register bit
15 to a one. The required filter length is then selected using
control register bits 14 and 13 as summarised in Table 3. The
options define the number of times each multiplier accumulator
is used per sample clock period. This can be once, twice, four
times, or eight times.
In addition a normal/decimate bit (CR12) allows the filter
length to be doubled at any sample rate. This is possible when
the filter coefficients are selected to produce a low pass filter,
since the filtered output would then not contain the higher
frequency components present in the input. The Nyquist
criterion, specifying that the sampling rate must be at least
double the highest frequency component, can still then be
satisfied even though the sampling rate has been halved.
CR
14 13 12
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Input
Rate
SCLK
SCLK
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
Output
Rate
SCLK
SCLK/2
SCLK/2
SCLK/4
SCLK/4
SCLK/8
SCLK/8
Filter
Length
16 Taps
32 Taps
32 Taps
64 Taps
64 Taps
128 Taps
128 Taps
Setup
Latency
16
17
16
18
20
24
24
The system clock latency for a single device is shown in
Table 3. This is defined as the delay from a particular data
sample being available on the input pins to the first result
including that input appearing on the output pins. It does not
include the delay needed to gather N samples, for an N tap filter,
before a mathematically correct result is obtained.
DA15:0
F31:0
OEN
NETWORK
A
DUAL
MODE
MUX
NETWORK
B
SINGLE
MODE
DB15:0
X31:0
Table 3 Single Filter options
Fig. 5 Single Filter bus utilisation
5
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