935280617132 datasheet, PDF - EEWORLD Datasheet

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935280617132: DescriptionAUP/ULP/V SERIES, 3-INPUT OR-AND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-252, SOT-886, SON-6; Categorylogic logic; File Size125KB，19 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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935280617132 Overview

AUP/ULP/V SERIES, 3-INPUT OR-AND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-252, SOT-886, SON-6

935280617132 Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	VSON,
Reach Compliance Code	unknow
series	AUP/ULP/V
JESD-30 code	R-PDSO-N6
JESD-609 code	e3
length	1.45 mm
Logic integrated circuit type	OR-AND GATE
Number of functions	1
Number of entries	3
Number of terminals	6
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	VSON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)	20.1 ns
Maximum seat height	0.5 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	0.8 V
Nominal supply voltage (Vsup)	1.1 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	TIN
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
width	1 mm

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74AUP1G3208

Low-power 3-input OR-AND gate

Rev. 4 — 23 November 2011

Product data sheet

1. General description

The 74AUP1G3208 provides the Boolean function: Y = (A + B)



C. The user can choose

the logic functions OR, AND and OR-AND. All inputs can be connected to V

or GND.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD 78 Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial Power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

935280617132 Related Products

	935280617132	74AUP1G3208GF/S500,132	935280616125	935280617115
Description	AUP/ULP/V SERIES, 3-INPUT OR-AND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-252, SOT-886, SON-6	OR-AND Gate, AUP/ULP/V Series, 1-Func, 3-Input, CMOS, PDSO6	AUP/ULP/V SERIES, 3-INPUT OR-AND GATE, PDSO6, PLASTIC, SOT-363, SC-88, 6 PIN	AUP/ULP/V SERIES, 3-INPUT OR-AND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-252, SOT-886, SON-6
Maker	NXP	NXP	NXP	NXP
package instruction	VSON,	VSON,	TSSOP,	VSON,
Reach Compliance Code	unknow	unknown	unknow	unknow
series	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V	AUP/ULP/V
JESD-30 code	R-PDSO-N6	S-PDSO-N6	R-PDSO-G6	R-PDSO-N6
length	1.45 mm	1 mm	2 mm	1.45 mm
Logic integrated circuit type	OR-AND GATE	OR-AND GATE	OR-AND GATE	OR-AND GATE
Number of functions	1	1	1	1
Number of entries	3	3	3	3
Number of terminals	6	6	6	6
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VSON	VSON	TSSOP	VSON
Package shape	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)	20.1 ns	20.1 ns	20.1 ns	20.1 ns
Maximum seat height	0.5 mm	0.5 mm	1.1 mm	0.5 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	0.8 V	0.8 V	0.8 V	0.8 V
Nominal supply voltage (Vsup)	1.1 V	1.1 V	1.1 V	1.1 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal form	NO LEAD	NO LEAD	GULL WING	NO LEAD
Terminal pitch	0.5 mm	0.35 mm	0.65 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	1 mm	1 mm	1.25 mm	1 mm
JESD-609 code	e3	-	e3	e3
Terminal surface	TIN	-	TIN	TIN

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