74LVC244A-Q100;
74LVCH244A-Q100
Quad buffer/line driver; 3-state
Rev. 2 — 13 August 2013
Product data sheet
1. General description
The 74LVC244A-Q100; 74LVCH244A-Q100 is an octal non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE
and 2OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation, outputs can
handle 5 V. These features allow the use of these devices as translators in a mixed
3.3 V and 5 V environment.
The 74LVCH244A-Q100 bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
CC
= 0 V
Bus hold on all data inputs (74LVCH244A-Q100 only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74LVC244A-Q100; 74LVCH244A-Q100
Quad buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC244AD-Q100
74LVCH244AD-Q100
74LVC244ADB-Q100
74LVCH244ADB-Q100
74LVC244APW-Q100
74LVCH244APW-Q100
74LVC244ABQ-Q100
74LVCH244ABQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP20
40 C
to +125
C
SSOP20
40 C
to +125
C
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20
leads; body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
Type number
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5
4.5
0.85 mm
4. Functional diagram
2
18
17
3
1A0
1Y0
2A0
2Y0
1A1
4
16
1Y1
2A1
15
5
2Y1
1A2
6
14
1Y2
2A2
13
7
2Y2
1A3
1OE
8
1
12
1Y3
2A3
2OE
11
19
9
2Y3
mna874
Fig 1.
Logic symbol
74LVC_LVCH244A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 13 August 2013
2 of 18
NXP Semiconductors
74LVC244A-Q100; 74LVCH244A-Q100
Quad buffer/line driver; 3-state
2
1A0
1Y0
18
4
1A1
1Y1
16
6
1A2
1Y2
14
1
EN
18
16
14
12
8
1
1A3
1OE
1Y3
12
2
4
6
8
17
2A0
2Y0
3
15
19
EN
13
11
13
15
17
mna873
2A1
2Y1
5
2A2
2Y2
7
9
7
5
3
19
11
2A3
2OE
2Y3
9
mna875
Fig 2.
IEC logic diagram
Fig 3.
Functional diagram
74LVC_LVCH244A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 13 August 2013
3 of 18
NXP Semiconductors
74LVC244A-Q100; 74LVCH244A-Q100
Quad buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO20 and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20
5.2 Pin description
Table 2.
Symbol
1OE, 2OE
1A0, 1A1, 1A2, 1A3
2Y0, 2Y1, 2Y2, 2Y3
GND
2A0, 2A1, 2A2, 2A3
1Y0, 1Y1, 1Y2, 1Y3,
V
CC
Pin description
Pin
1, 19
2, 4, 6, 8
3, 5, 7, 9
10
Description
output enable input (active low)
data input
data output
ground (0 V)
17, 15, 13, 11 data input
18, 16, 14, 12 data output
20
supply voltage
74LVC_LVCH244A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 13 August 2013
4 of 18
NXP Semiconductors
74LVC244A-Q100; 74LVCH244A-Q100
Quad buffer/line driver; 3-state
6. Functional description
Table 3.
Control
nOE
L
L
H
[1]
Function table
[1]
Input
nAn
L
H
X
Output
nYn
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 packages: above 70
C
derate linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
C
derate linearly with 4.5 mW/K.
74LVC_LVCH244A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 13 August 2013
5 of 18
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