935325938557 datasheet, PDF - EEWORLD Datasheet

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935325938557: DescriptionRISC Microprocessor; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，237 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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935325938557 Overview

RISC Microprocessor

935325938557 Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	,
Reach Compliance Code	unknow
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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NXP Semiconductors

Data Sheet: Technical Data

Document Number T4240

Rev. 1, 05/2016

QorIQ T4240 Data Sheet

Features

• 12 e6500 cores built on Power Architecture®

technology and arranged as clusters of four e6500

cores sharing a 2 MB L2 cache

• 1.5 MB CoreNet platform cache (CPC)

• Hierarchical interconnect fabric

– CoreNet fabric supporting coherent and non-

coherent transactions with prioritization and

bandwidth allocation amongst CoreNet end-points

– 1.6 Tbps coherent read bandwidth

• Three 64-bit DDR3 SDRAM memory controllers

– DDR3 and DDR3L with ECC and interleaving

support

• Data Path Acceleration Architecture (DPAA)

incorporating acceleration for the following functions:

– Packet parsing, classification, and distribution

(Frame Manager 1.1)

– Queue management for scheduling, packet

sequencing, and congestion management (Queue

Manager 1.1)

– Hardware buffer management for buffer allocation

and de-allocation (Buffer Manager 1.1)

– Cryptography Acceleration (SEC 5.0)

– RegEx Pattern Matching Acceleration (PME 2.0)

– Decompression/Compression Acceleration (DCE

1.0)

– DPAA chip-to-chip interconnect via RapidIO

Message Manager (RMan 1.0)

T4240

• 32 SerDes lanes at up to 10 Gb/s

• Ethernet interfaces

– Up to four 10 Gbps Ethernet MACs

– Up to sixteen 1 Gbps Ethernet MACs

– Combinations of 1 Gbps and 10 Gbps Ethernet

MACs

– IEEE Std 1588™ support

• High-speed peripheral interfaces

– Four PCI Express 2.0/3.0 controllers running at up

to 8 GT/s with one controllers supporting end-point,

single-root I/O virtualization (SR-IOV)

– Two Serial RapidIO 2.0 controllers running at up to

5 Gbaud

– Interlaken look-aside interface for TCAM

connection

• Additional peripheral interfaces

– Two Serial ATA (SATA 2.0) controllers

– Two high-speed USB 2.0 controllers with integrated

PHY

– Enhanced secure digital host controller (SD/MMC/

eMMC)

– Enhanced Serial peripheral interface (eSPI)

– Four I2C controllers

– Four 2-pin UARTs or two 4-pin DUARTs

– Integrated flash controller supporting NAND and

NOR flash

• Three 8-channel DMA engines

• 1932 FC-PBGA package, 45 mm x 45 mm, 1mm pitch

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1 Overview.............................................................................................. 3

2 Pin assignments.................................................................................... 3

2.1

2.2

1932 ball layout diagrams......................................................... 4

Pinout list...................................................................................10

3.16 JTAG controller.........................................................................124

3.17 I2C interface.............................................................................. 127

3.18 GPIO interface...........................................................................130

3.19 High-speed serial interfaces (HSSI).......................................... 132

4 Hardware design considerations...........................................................188

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

System clocking........................................................................ 188

Power supply design..................................................................204

Decoupling recommendations................................................... 213

SerDes block power supply decoupling recommendations.......213

Connection recommendations................................................... 214

Thermal......................................................................................225

Recommended thermal model...................................................226

Thermal management information............................................ 226

3 Electrical characteristics.......................................................................73

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Overall DC electrical characteristics......................................... 73

Power sequencing......................................................................80

Power-down requirements.........................................................82

Power characteristics................................................................. 83

Power-on ramp rate................................................................... 90

Input clocks............................................................................... 91

RESET initialization..................................................................96

DDR3 and DDR3L SDRAM controller.................................... 97

eSPI interface.............................................................................103

5 Package information.............................................................................229

5.1

5.2

Package parameters for the FC-PBGA......................................229

Mechanical dimensions of the FC-PBGA................................. 229

3.10 DUART interface...................................................................... 106

3.11 Ethernet interface, Ethernet management interface 1 and 2,

IEEE Std 1588........................................................................... 107

3.12 USB interface............................................................................ 116

3.13 Integrated flash controller..........................................................118

3.14 Enhanced secure digital host controller (eSDHC).....................121

3.15 Multicore programmable interrupt controller (MPIC).............. 123

6 Security fuse processor.........................................................................231

7 Ordering information............................................................................231

7.1

7.2

Part numbering nomenclature....................................................231

Orderable part numbers addressed by this document................232

8 Revision history....................................................................................234

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

935325938557 Related Products

	935325938557	935318925557	935313375557	935323888557	935324898557	935325106557	935318887557	935324764557	935322113557
Description	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor	RISC Microprocessor
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Reach Compliance Code	unknow	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	-	1	1	1	1	1	1	1	-

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