UM10326
LPC32x0 and LPC32x0/01 User manual
Rev. 3 — 22 July 2011
User manual
Document information
Info
Keywords
Abstract
Content
LPC3220, LPC3230, LPC3240, LPC3250, ARM9, LPC3220/01,
LPC3230/01, LPC3240/01, LPC3250/01, 16/32-bit ARM microcontroller.
User manual for LPC32x0.
NXP Semiconductors
UM10326
LPC32x0 User manual
Revision history
Rev
3
Date
20110722
Description
LPC32x0 user manual
Modifications: System control chapter added.
2
20110504
LPC32x0 user manual
Modifications:
•
•
•
•
•
•
•
•
•
•
•
•
•
1
20090218
Voltage domains updated in Table 671, Table 696, and Table 697.
LCDENAB signal updated in LCD timing diagrams Figure 35 and Figure 36.
Definition of Bus Keeper (BK) pins updated in Table 670.
GPI_6 updated to input with bus keeper function.
Power supply domain for pins SYSX_IN and SYSX_OUT updated in Table 671.
Description of DBGEN pin function updated in Section 4.6.1 and Table 671.
Explanation of simultaneous update mode for PWM Motor control Match and Limit
register added in Section 30.7.7.1 “Match and Limit shadow write and operating
registers”.
Registers SERIAL_ID0 to 3 added for unique serial ID number (Section 3.1.3).
Updated TAP ID and ETB ID (Table 710).
Editorial updates.
Pin functions for touch screen control controller updated: pin T14 has functions
ADIN1/TS_XM and pin U15 has functions ADIN0/TS_YM (see Table 668, Table 669,
Table 255, Table 229, Figure 37.
Pin selection for touch screen control controller in manual mode updated (TS_YPC
values in Table 231).
Parts LPC3220/01, LPC3230/01, LPC3240/01, LPC3250/01 added.
Initial LPC32x0 user manual release.
Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
User manual
Rev. 3 — 22 July 2011
2 of 721
UM10326
Chapter 1: LPC32x0 Introductory information
Rev. 3 — 22 July 2011
User manual
1.1 Introduction
NXP Semiconductor designed the LPC32x0 for embedded applications requiring high
performance and low power consumption.
NXP achieved their performance objectives using an ARM926EJ-S CPU core with a
Vector Floating Point co-processor and a large set of standard peripherals, including USB
On-The-Go. Figure 1 shows a block diagram of the LPC32x0. The LPC32x0 operates at
CPU frequencies up to 266 MHz. The basic ARM926EJ-S CPU Core implementation uses
a Harvard architecture with a 5-stage pipeline. The ARM926EJ-S core also has an
integral Memory Management Unit (MMU) to provide the virtual memory capabilities
required to support the multi-programming demands of modern operating systems. The
basic ARM926EJ-S core also includes a set of DSP instruction extensions including single
cycle MAC operations and native Jazelle Java Byte-code execution in hardware. The NXP
implementation has one 32 kB Instruction Cache and one 32 kB Data Cache.
For low power consumption, the LPC32x0 takes advantage of NXP Semiconductor's
advanced technology development expertise to optimize Intrinsic Power, and software
controlled architectural enhancements to optimize Power Management.
The LPC32x0 also includes 128 to 256 kB of on-chip static RAM, a NAND Flash interface,
an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external
bus interface that supports SDR and DDR SDRAM as well as static devices. In addition,
the LPC32x0 includes a USB 2.0 Full Speed interface, seven UARTs, two I2C interfaces,
two SPI/SSP ports, two I2S interfaces, two single output PWMs, a motor control PWM,
four general purpose timers with capture inputs and compare outputs, a Secure Digital
(SD) interface, and a 10-bit A/D converter with a touch screen sense option.
UM10326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
User manual
Rev. 3 — 22 July 2011
3 of 721
NXP Semiconductors
UM10326
Chapter 1: LPC32x0 Introductory information
External
Memory
Interfaces
CPU subsystem
ETB
ETM9
I-Cache
32kB
D-Cache
32kB
VFP9
NAND
Flash
On-Chip
Memory
ROM
256 kB
SRAM
SD Card
SRAM and
SDRAM
(SDR/
DDR)
control
ARM926EJ
Instr
Data
Bus matrix (Multi-layer AHB )
Interrupt
Controller
System
Control
PLLs
Power
Control
DMA
Controller
Watchdog
High Speed
Timer
Millisecond
Timer
Timer
0,1,2,3,4,5
LCD
GPIO
Keyscan
Touch
Screen /
10-bit A/D
RTC
PWM 1, 2
Motor
Control
PWM
Ethernet
MAC
UART
1-5, 7
USB OTG
I2C 1, 2
I2S 0, 1
UART6
IrDA
SPI 1, 2
SSP 0, 1
System Functions
Fig 1.
LPC32x0 diagram
Other
Peripherals
Communication
Peripherals
UM10326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
User manual
Rev. 3 — 22 July 2011
4 of 721
NXP Semiconductors
UM10326
Chapter 1: LPC32x0 Introductory information
1.2 Features
•
•
•
•
•
ARM926EJS processor, running at CPU clock speeds up to 266 MHz
A Vector Floating Point coprocessor.
A 32 kB instruction cache and a 32 kB data cache.
Up to 256 kB of internal SRAM.
Selectable boot-up from various external devices: NAND Flash, SPI memory, USB,
UART, or static memory.
including both an instruction and data bus for the CPU, two data busses for the DMA
controller, and another bus for the USB controller, one for the LCD and a final one for
the Ethernet MAC. There are no arbitration delays in the system unless two masters
attempt to access the same slave at the same time.
•
A Multi-layer AHB system that provides a separate bus for each AHB master,
•
An External memory controller for DDR and SDR SDRAM, as well as static devices.
–
The address bus provides up to 16 MB for each of the 4 static chip selects.
–
The controller provides two dynamic memory chip selects addressing up to
512 MB each.
•
Two NAND Flash controllers. One for single level NAND Flash devices and the other
for multi-level NAND Flash devices.
•
An Interrupt Controller, supporting 73 interrupt sources.
•
An eight channel General Purpose AHB DMA controller (GPDMA) that can be used
with the SD card port, the 14-clock UARTs, I2S ports, and SPI interfaces, as well as
memory-to-memory transfers.
•
Serial Interfaces:
–
A 10/100 Ethernet MAC with dedicated DMA Controller.
–
A USB interface supporting either Device, Host (OHCI compliant), or On-The-Go
(OTG) with an integral DMA controller and dedicated PLL to generate the required
48 MHz USB clock.
–
Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One
of the standard UART’s supports IrDA.
–
Three additional 14-clock UARTs intended for on-board communications that
support baudrates up to 921,600 bps when using a 13 MHz main oscillator.All
14-clock UARTs provide 64-byte FIFOs.
–
Two SPI controllers.
–
Two SSP controllers.
–
Two I2C-bus Interfaces with standard open drain pins. The I2C-bus Interfaces
support single master, slave and multi-master I2C configurations.
–
Two I2S interfaces, each with separate input and output channels. Each channel
can be operated independently on 3 pins, or both input and output with one I2S
interface can be done on only 4 pins.
•
Additional Peripherals:
–
LCD controller supporting both STN and TFT panels, with dedicated DMA
controller. Programmable display resolution up to 1024x768.
–
Secure Digital (SD) memory card interface.
UM10326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
User manual
Rev. 3 — 22 July 2011
5 of 721
京公网安备 11010802033920号
EEWORLD
