®
THD218DHI
HIGH VOLTAGE FAST-SWITCHING
NPN POWER TRANSISTOR
s
s
s
s
STMicroelectronics PREFERRED
SALESTYPE
HIGH VOLTAGE CAPABILITY
U.L. RECOGNISED ISOWATT218 PACKAGE
(U.L. FILE # E81734 (N))
NPN TRANSISTOR WITH INTEGRATED
FREEWHEELING DIODE.
3
2
1
APPLICATIONS
s
HORIZONTAL DEFLECTION FOR COLOUR
TV
DESCRIPTION
This devices is manufactured using Multiepitaxial
Mesa technology for cost-effective high
performance and uses a Hollow Emitter structure
to enhance switching speeds.
The THD series is designed for use in horizontal
deflection circuits in televisions and monitors.
ISOWATT218
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
B
I
BM
P
t ot
T
stg
T
j
Parameter
Collector-Base Voltage (I
E
= 0)
Collector-Emitter Voltage (I
B
= 0)
Emitter-Base Voltage (I
C
= 0)
Collector Current
Collector Peak Current (t
p
< 5 ms)
Base Current
Base Peak Current (t
p
< 5 ms)
Total Dissipation at T
c
= 25 C
St orage Temperature
Max. Operating Junction Temperature
o
Value
1500
700
10
7
12
4
7
50
-65 to 150
150
Uni t
V
V
V
A
A
A
A
W
o
o
C
C
December 1999
1/6
THD218DHI
THERMAL DATA
R
t hj-ca se
Thermal Resistance Junction-case
Max
2.5
o
C/W
ELECTRICAL CHARACTERISTICS
(T
case
= 25
o
C unless otherwise specified)
Symb ol
I
CES
I
EBO
V
CE(sat )
∗
V
BE(s at)
∗
h
FE
∗
Parameter
Collector Cut-off
Current (V
BE
= 0)
Emitter Cut-off Current
(I
C
= 0)
Collector-Emitter
Saturation Voltage
Base-Emitter
Saturation Voltage
DC Current G ain
INDUCTIVE LOAD
Storage Time
Fall T ime
Test Cond ition s
V
CE
= 1500 V
V
CE
= 1500 V
V
EB
= 5 V
I
C
= 4 A
I
C
= 4 A
I
C
= 4 A
I
C
= 4 A
I
C
= 4 A
I
B1
= 1 A
V
CE
= 5 V
V
CE
= 5 V
I
B
= 1 A
I
B
= 1 A
5
3.5
4.7
0.48
T
j
= 125 C
o
Min.
Typ .
Max.
0.2
2
300
1.5
1.3
10
Un it
mA
mA
mA
V
V
T
j
= 100 C
o
t
s
t
f
f = 15625 Hz
I
B2
= -2 A
π
6
V
c eflybac k
= 1050 sin
10
t
5
I
F
= 4 A
V
µs
µs
V
F
Diode Forward Voltage
2.5
V
∗
Pulsed: Pulse duration = 300
µs,
duty cycle 1.5 %
Safe Operating Area
Thermal Impedance
2/6
THD218DHI
Reverse Biased SOA
BASE DRIVE INFORMATION
In order to saturate the power switch and reduce
conduction losses, adequate direct base current
I
B1
has to be provided for the lowest gain h
FE
at
100
o
C (line scan phase). On the other hand,
negative base current I
B2
must be provided to
turn off the power transistor (retrace phase).
Most of the dissipation, in the deflection
application, occurs at switch-off. Therefore it is
essential to determine the value of I
B2
which
minimizes power losses, fall time t
f
and,
consequently, T
j
. A new set of curves have been
defined to give total power losses, t
s
and t
f
as a
function of I
B2
at both 16 KHz and 32 KHz
scanning frequencies for choosing the optimum
negative drive. The test circuit is illustrated in
Figure 1:
Inductive Load Switching Test Circuit.
figure 1.
Inductance L
1
serves to control the slope of the
negative base current I
B2
to recombine the
excess carrier in the collector when base current
is still present, this would avoid any tailing
phenomenon in the collector current.
The values of L and C are calculated from the
following equations:
1
1
1
L
(
I
C
)
2
=
C
(
V
CEfly
)
2
ω =
2
π
f
=
2
2
L
√
C
Where I
C
= operating collector current, V
CEfly
=
flyback voltage, f= frequency of oscillation during
retrace.
4/6
51mcu
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