Application Report
SZZA034 - September 2002
TI IBIS File Creation, Validation, and Distribution Processes
Moshiul Haque
ABSTRACT
The Input/Output Buffer Information Specification (IBIS), also known as ANSI/EIA-656, has
become widely accepted among electronic design automation (EDA) vendors,
semiconductor vendors, and system designers as the format for digital electrical interface
data. Because IBIS models do not reveal proprietary, internal processes, or architectural
information, semiconductor vendors’ support for IBIS continues to grow. IBIS models are one
of the most important tools used to support TI customers. TI’s goal is to create IBIS models
that are compatible with the latest IBIS specifications for every new logic part. This application
report describes TI’s IBIS creation, validation, and distribution process, so that customers
can be better informed about our IBIS models. This application report also discusses the
accuracy of IBIS models provided by TI.
Standard Linear & Logic
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 What is IBIS? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 History of IBIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 IBIS and SPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
2
Brief Description of Some Common Types of IBIS Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Input Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 2-State Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 3-State Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Input/Output Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Open-Drain Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IBIS Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 SPICE Simulation Setup for IBIS Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 Pullup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2 Pulldown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.3 Ground Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.4 Power Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.5 Ramp, Rising, and Falling Waveform Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.6 C_comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 IBIS File Data Extraction and Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IBIS File Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Visual Check of IBIS Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Pullup Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Pulldown Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Rising Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
4
5
Trademarks are the property of their respective owners.
1
SZZA034
5.4
5.5
5.6
5.7
6
7
8
9
Falling Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ground-Clamp Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus-Hold Behavior in Ground-Clamp Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-Clamp Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IBIS File Warnings and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IBIS File Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Appendix-A. Using IBIS Model in HSPICE Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Input Model Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Test Simulation Setup to Compare the Difference in Voltage Waveforms
Due to R_fixture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Comparison of Voltage Waveforms for IBIS Model Created
With 50-Ω and 500-Ω Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V_fixture, R_fixture, C_fixture, and L_fixture in AC Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Two-State Output Model Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Rref, Cref, and Vref During Propagation Delay Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data-Sheet Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Parameter-Measurement Information for GTLP Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Vmeas in Propagation Delay Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3-State Output Model Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input/Output Buffer Model Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPICE Setup to Extract Pullup Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPICE Setup to Extract Pulldown Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPICE Setup for V-T data (R_fixture Connected to Pullup Reference) . . . . . . . . . . . . . . . 15
SPICE Setup for V-T Data (R_fixture Connected to Pulldown Reference) . . . . . . . . . . . . 16
SPICE Setup to Measure C_comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pullup Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pulldown Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rising Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Falling Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ground-Clamp Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bus-Hold Behavior in Ground-Clamp Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-Clamp Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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TI IBIS File Creation, Validation, and Distribution Processes
SZZA034
1
1.1
Introduction
What is IBIS?
The input/output buffer information specification (IBIS) is a behavioral-modeling specification. It
is a standard for describing the analog behavior of the buffers of a digital device using plain
ASCII-text formatted data. The data in an IBIS file is used to perform signal integrity (SI)
simulations of printed circuit boards. The information needed to perform this simulation is buffer
voltage-current (V-I) characteristics and switching (output voltage versus time) characteristics.
1.2
History of IBIS
IBIS was created in the early 1990s to promote tool-independent I/O models for system-level
signal-integrity work. PCI bus signal-integrity simulations were ramping up at Intel , but no one
had a PCI buffer designed. In general, SPICE models were not commonly available. To
overcome this problem, Intel developed a behavioral buffer model in HSPICE that simulates
any buffer characteristics. The behavioral model was so successful that Intel decided to supply
it to customers. But, all customers did not use HSPICE, so a tool-independent model format was
needed. Several electronic design automation (EDA) tool vendors showed interest in a common
modeling format, and the IBIS open forum was formed. The first IBIS specification, 1.0, was
released in April 1993.
t
t
t
1.3
Input Model
SPICE models are the most widely used models. SPICE models are based on transistor-level
modeling. For complicated electronic circuits, the total time required to complete a simulation in
SPICE is long. SPICE models also should be encrypted, or there should be a nondisclosure
agreement (NDA) in place to protect proprietary information. On the other hand, IBIS is a
behavioral model and does not reveal any proprietary information. Because IBIS is a behavioral
model, the total time for simulation is much less than for SPICE.
2
Brief Description of Some Common Types of IBIS Models
An IBIS file of a device contains the electrical characteristics of all the unique pins of that device.
Electrical characteristics of a specific pin are called an IBIS model of that pin. An IBIS file also
contains the package resistance, inductance, and capacitance (R, L, and C) data for each pin.
The following are the most common types of pins in a digital-logic device:
•
•
•
•
•
Input
2-state output
3-state output
Input/output (I/O)
Open drain
Similarly, the model in an IBIS file can be input, 3-state, I/O, etc.
TI IBIS File Creation, Validation, and Distribution Processes
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SZZA034
2.1
Input Model
The input pin structure of a digital device can be thought of as a combination of the following
circuits and elements.
•
•
•
•
•
A circuit that is activated if the input voltage is over V
CC
or logic high (power clamp)
A circuit that is activated if the input voltage is below ground or logic low (ground clamp)
A circuit that is activated if the input is within V
CC
and ground (active circuit)
Resistance, inductance, and capacitance of the package (R, L, and C)
Die capacitance of the input pin
The data for these circuits and elements are described under several keywords in the IBIS file.
IBIS keywords are shown in square brackets.
The behavior of the first circuit is listed under the [POWER Clamp] keyword, and the behaviors
of the latter two circuits are listed under the [GND Clamp] keyword. R, L, and C are listed under
the [Pin] keyword. Most often, a CMOS digital device has the input structure shown in Figure 1.
In this input structure, V
DD
is the power-clamp reference because the upper clamp diode is
connected to the dc voltage source V
DD†
, and –V
SS†
is the ground-clamp reference because the
lower clamp diode is connected to the dc voltage source –V
SS
. The details of power-clamp and
the ground-clamp references are discussed later in this application report. Even though the
package R, L, and C data are included for the input pin, the ground-clamp and power-clamp
data for the IBIS model are extracted without package data; i.e., package R, L, and C do not
have any effect on this data.
VDD
VDD
L_pkg
R_pkg
Input
C_pkg
C_comp
To Internal Circuit
–VSS
–VSS –VSS
–VSS
Figure 1. Input Model Structure
The upper clamp diode is forward biased when the input is approximately 0.7 V over V
DD
. The
lower clamp diode is forward biased when the input is approximately 0.7 V less than –V
SS
.
† VDD is equivalent to VCC or power supply and –VSS is equivalent to GND in TI digital logic devices.
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TI IBIS File Creation, Validation, and Distribution Processes
SZZA034
The input-type model has the following data. Subparameters are enclosed in parentheses.
•
•
•
Maximum lower threshold voltage (Vinl): V
IL
in the data sheet.
Minimum upper threshold voltage (Vinh): V
IH
in the data sheet.
Power-clamp reference [Power Clamp Reference]: In most digital circuits, the power-clamp
reference voltage is V
CC
because the power-clamp diode is connected to V
CC
. However, in
some cases it may be different than the V
CC
or power supply. For example, with 5-V safe
3.3-V buffers, the power-clamp reference is 5 V.
Ground-clamp reference [GND Clamp Reference]: In most digital circuits, the ground-clamp
reference voltage is 0. However, in some cases it may be different than the ground. For
example, in RS-232 devices it is –12 V.
Recommended power supply [Voltage Range].
Recommended temperature [Temperature Range]: The junction temperature of transistors.
C_comp data (C_comp): This is the total die capacitance as seen at the die pad. C_comp
does not include package capacitance. It includes parasitic capacitance of transistors and
circuit elements, metal capacitance-connecting transistors with the die pad, and die-pad
capacitance.
Power-clamp data [
POWER Clamp]
: Voltage-current characteristics of the power-clamp
circuit. This data is referenced to the power-clamp reference voltage, i.e., in the IBIS file the
power clamp voltage is V
table
= [Power Clamp Reference] – V
in
, where V
in
is the voltage
referenced to ground. For example, if power-clamp reference is V
CC
, then the voltage data in
IBIS file is V
table
= V
CC
– V
in
. This is the voltage across the diode, not the input voltage.
Ground-clamp data [GND Clamp]: Voltage-current characteristics of the ground-clamp
circuit. This data is referenced to ground-clamp reference voltage, i.e., in an IBIS file the
ground-clamp voltage is V
table
= V
in
– [GND Clamp Reference], where V
in
is the voltage
referenced to ground. For example, if the ground-clamp reference is ground, the voltage
data in the IBIS file is V
table
= V
in
.
•
•
•
•
•
•
If the power-clamp reference voltage is not mentioned, then, by default, it is equal to the
recommended power-supply voltage. Similarly, if the ground-clamp reference voltage is not
mentioned, then, by default, it is equal to ground or 0.
The range of data is based on the worst-case scenario of a transmission line. For example, a
device with a power-clamp reference of V
DD
and a ground-clamp reference of –V
SS
has a
maximum voltage of (2
×
V
DD
+ V
SS
) and minimum voltage of –(2
×
V
SS
+ V
DD
).
The power-clamp diode is on from V
DD
to maximum voltage; i.e., 2
×
V
DD
+ V
SS
. As in the IBIS
file, power-clamp data is V
DD
relative, so the range would be –(V
DD
+ V
SS
) to 0 (V
table
=
[(power-clamp reference voltage) – V
in
]). Ground-clamp diode data range from –(2
×
V
SS
+ V
DD
)
to V
DD
. In the IBIS file, the data ranges from –(V
SS
+ V
DD
) to (V
DD
+ V
SS
) (V
table
= V
in
–
ground-clamp reference voltage).
So, for a 5-V V
CC
device, the range of ground-clamp data in the IBIS file is from –5 V to 5 V, and
for power-clamp data, the range is –5 V to 0 V. There may be a question of why the range of
ground-clamp data is from –5 V to 5 V, since the diode is forward biased only from –5 V to 0,
and from 0 to 5 V, the diode is reverse biased. The reason is that, even though it is designated
as ground clamp, the data also contains the V-I data at the normal operating conditions. For
example, if IBIS users need to know what the input current at threshold is or what the bus-hold
current is, they can get it from the ground-clamp data.
TI IBIS File Creation, Validation, and Distribution Processes
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