UDIMM
DDR2 SDRAM
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 1Gb Q-die
64/72-bit Non-ECC/ECC
60FBGA & 84FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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UDIMM
Table of Contents
DDR2 SDRAM
1.0 DDR2 Unbuffered DIMM Ordering Information ..........................................................................4
2.0 Features .........................................................................................................................................4
3.0 Address Configuration .................................................................................................................4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................5
5.0 x72 DIMM Pin Configurations (Front side/Back side) ................................................................6
6.0 Pin Description ..............................................................................................................................6
7.0 Input/Output Function Description .............................................................................................7
8.0 Functional Block Diagram : .........................................................................................................8
8.1 1GB, 128Mx64 Module - M378T2863QZ(H)S
......................................................................................8
8.2 1GB, 128Mx72 ECC Module - M391T2863QZ(H)3
................................................................................9
8.3 2GB, 256Mx64 Module - M378T5663QZ(H)3
.....................................................................................10
8.4 2GB, 256Mx72 ECC Module - M391T5663QZ(H)3
..............................................................................11
8.5 512MB, 64Mx64 Module - M378T6464QZ(H)3
...................................................................................12
9.0 Absolute Maximum DC Ratings .................................................................................................13
10.0 AC & DC Operating Conditions ...............................................................................................13
....................................................................13
10.2 Operating Temperature Condition
................................................................................................14
10.3 Input DC Logic Level
..................................................................................................................14
10.4 Input AC Logic Level
..................................................................................................................14
10.5 AC Input Test Conditions
............................................................................................................14
11.0 IDD Specification Parameters Definition ................................................................................15
12.0 Operating Current Table : .........................................................................................................16
12.1 M378T2863QZ(H)S : 1GB(128Mx8 *8) Module
................................................................................16
12.2 M378T5663QZ(H)3 : 2GB(128Mx8 *16) Module
..............................................................................16
12.3 M391T2863QZ(H)3 : 1GB(128Mx8 *9) ECC Module
..........................................................................17
12.4 M391T5663QZ(H)3 : 2GB(128Mx8 *18) ECC Module
........................................................................17
10.1 Recommended DC Operating Conditions (SSTL - 1.8)
.............................................................................18
13.0 Input/Output Capacitance ........................................................................................................19
14.0 Electrical Characteristics & AC Timing for DDR2-800/667 ....................................................19
12.5 M378T6464QZ(H)3 : 512MB(64Mx16 *4) Module
.........................................................................................19
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
..............................................19
14.3 Timing Parameters by Speed Grade
.............................................................................................20
15.0 Physical Dimensions : ..............................................................................................................22
15.1 128Mbx8 based 128Mx64 Module (1 Rank)
....................................................................................22
15.2 128Mbx8 based 128M x72 Module (1 Rank)
...................................................................................23
15.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks)
.............................................................................24
15.4 64Mbx16 based 64Mx64 Module (1 Rank)
......................................................................................25
14.1 Refresh Parameters by Device Density
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1.0 DDR2 Unbuffered DIMM Ordering Information
Part Number
M378T2863QZ(H)S-CE7/F7/E6
M378T5663QZ(H)3-CE7/F7/E6
M378T6464QZ(H)3-CE7/F7/E6
M391T2863QZ(H)3-CE7/F7/E6
M391T5663QZ(H)3-CE7/F7/E6
Density
1GB
2GB
512MB
1GB
2GB
Organization
128Mx64
256Mx64
64Mx64
x72 ECC
128Mx72
256Mx72
128Mx8(K4T1G084QQ)*9
128Mx8(K4T1G084QQ)*18
Component Composition
128Mx8(K4T1G084QQ)*8
128Mx8(K4T1G084QQ)*16
64Mx16(K4T1G164QQ)*4
DDR2 SDRAM
Number of Rank
1
2
1
1
2
Height
30mm
30mm
30mm
30mm
30mm
x64 Non ECC
Note :
1. “Z” of Part number(12th digit) stands for Lead-Free and RoHS compliant products.
2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
3. “3” of Part number(13th digit) stands for Dummy Pad PCB products.
2.0 Features
• Performance range
E7 (DDR2-800)
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
400
533
800
-
5-5-5
F7 (DDR2-800)
-
533
667
800
6-6-6
E6 (DDR2-667)
400
533
667
-
5-5-5
Unit
Mbps
Mbps
Mbps
Mbps
CK
• JEDEC standard V
DD
= 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/Nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• Average Refresh Period 7.8us at lower than a T
CASE
85°C, 3.9us at 85°C < T
CASE
< 95
°C
-
Support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 128Mx8 and 84ball FBGA - 64Mx16
• All of base components are Lead-Free, Halogen-Free, and RoHS compliant
3.0 Address Configuration
Organization
128Mx8(1Gb) based Module
64Mx16(1Gb) based Module
Row Address
A0-A13
A0-A12
Column Address
A0-A9
A0-A9
Bank Address
BA0-BA2
BA0-BA2
Auto Precharge
A10
A10
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Microchip MCU
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