FBDIMM
DDR2 SDRAM
DDR2 Fully Buffered DIMM
240pin FBDIMMs based on 512Mb E-die
60FBGA with Lead-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.51 January 2008
FBDIMM
Table of Contents
DDR2 SDRAM
1. FEATURES .......................................................................................................................................4
2.0 FBDIMM GENERALS .....................................................................................................................5
2.1 FB-DIMM Operation Overview
..........................................................................................................5
2.2 FB-DIMM Channel Frequency Scaling
...............................................................................................6
2.3 FB-DIMM Clocking Scheme
.............................................................................................................7
..........................................................................................................................7
2.5 Southbound Command Delivery
......................................................................................................8
2.6 Basic Timing Diagram
.....................................................................................................................9
2.7 Advanced Memory Buffer Block Diagram
........................................................................................11
2.8 Interfaces
.................................................................................................................................... 12
3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE ...............12
3.1 DDR2 Channel
.............................................................................................................................12
3.2 SMBus Slave Interface
..................................................................................................................12
3.3 FBD Channel Latency
...................................................................................................................13
3.4 Peak Theoretical Throughput
.........................................................................................................13
2.4 FB-DIMM Protocol
.......................................................................................................................................13
3.6 Hot remove
..................................................................................................................................13
3.7 Hot replace
..................................................................................................................................13
4.0 PIN CONFIGUREATION ..............................................................................................................14
5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16
5.1 512MB, 64Mx72 Module - M395T6553EZ4
........................................................................................16
5.2 1GB, 128Mx72 Module - M395T2953EZ4
..........................................................................................17
5.3 2GB, 256Mx72 Module - M395T5750EZ4
..........................................................................................18
6.0 ELECTRICAL CHARACTERISTICS ............................................................................................19
7.0 CHANNEL INITIALIZATION ........................................................................................................27
3.5 Hot-add
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Rev. 1.51 January 2008
FBDIMM
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
1.5
1.51
Month
November
January
February
April
June
October
January
Year
2006
2007
2007
2007
2007
2007
2008
- First Released.
- Added AMB revision
History
DDR2 SDRAM
- Added IDT A1.5 FBD, Corrected DIMM Thickness(8.0mm to 8.2mm)
- Changed AMB device operation temperature symbol(Tj to Tcase)
- Added 800 FBD
- Added NEC D1 FBD, Removed NEC B5+ FBD
- Typo Correction
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Rev. 1.51 January 2008
FBDIMM
1. FEATURES
- 240pin fully buffered dual in-line memory module (FB-
DIMM)
- 3.2Gb/s, 4.0Gb/s, 4.8Gb/s link transfer rate
- 1.8V +/- 0.1V Power Supply for DRAM V
DD
/V
DDQ
- 1.5V +0.075/-0.045V Power Supply for AMB V
CC
- 3.3V +/- 0.3V Power Supply for V
DDSPD
- Buffer Interface with high-speed differential point-to-
point Link at 1.5 volt
- Channel error detection & reporting
-
-
-
-
-
-
-
-
-
DDR2 SDRAM
Channel fail over mode support
Serial presence detect with EEPROM
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5, 6
Automatic DDR2 DRAM bus and channel calibration
MBIST and IBIST Test functions
Hot add-on and Hot Remove Capability
Transparent mode for DRAM test support
Table 1 : Ordering Information
Part Number
M395T6553EZ4-CD55/E65
M395T6553EZ4-CD56/E66/F76/E76
M395T6553EZ4-CD51/E61
M395T6553EZ4-CD57/E67
M395T2953EZ4-CD55/E65
M395T2953EZ4-CD56/E66/F76/E76
M395T2953EZ4-CD51/E61
M395T2953EZ4-CD57/E67
M395T5750EZ4-CD55/E65
M395T5750EZ4-CD56/E66/F76/E76
M395T5750EZ4-CD51/E61
M395T5750EZ4-CD57/E67
Note :
1. “Z” of Part number(11th digit) stands for Lead-free products.
2. The last digit stands for AMB.
2GB
256M x 72
128Mx4(K4T51043QE)
* 36EA
2
1GB
128M x 72
64Mx8(K4T51083QE)
* 18EA
2
512MB
64M x 72
64Mx8(K4T51083QE)
* 9EA
1
Density
Organization
Component Composition
Number of
Rank
AMB
Intel D1
IDT C1
IDT A1.5
NEC D1
Intel D1
IDT C1
IDT A1.5
NEC D1
Intel D1
IDT C1
IDT A1.5
NEC D1
Full Module
30.35mm
Type of Heat
Spreader
Height
Table 2
:
Performance range
E7(DDR2-800)
DDR2 DRAM Speed
CL-tRCD-tRP
800
5-5-5
F7(DDR2-800)
800
6-6-6
E6(DDR2-667)
667
5-5-5
D5(DDR2-533)
533
4-4-4
Unit
Mbps
CK
Table 3 : Address Configuration
Organization
64Mx8(512Mb) based Module
128Mx4(512Mb) based Module
Row Address
A0-A13
A0-A13
Column Address
A0-A9
A0-A9, A11
Bank Address
BA0-BA1
BA0-BA1
Auto Precharge
A10
A10
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FBDIMM
2.0 FBDIMM GENERALS
2.1 FB-DIMM Operation Overview
DDR2 SDRAM
FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and
scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited
density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is intended to
eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to
a given channel.
Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new
technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with
packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differential
signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD
clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with
data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally all
FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to
Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.
Figure 1 shows a lot of new technologies integrated with FBD solution.
Figure 1 : FB-DIMM Memory System Overview
DRAM
Two unidirectional links
- Northbound
- Southbound
Protocol Packet
ADDR.CMD, DATA
DRAM
SB (ADDR, CMD, Wdata)
Host
NB(Rdata)
DQs ADDR CLK
CMD
Rx
Tx
Tx
AMB
Rx
Tx
Rx
AMB
Tx
Rx
CLK
Daisy Chain
Connection
Upto 8 AMB
Clk_Ref
ADDR
DQs CMD
P2P Interconnect
- LVDS
- De-Emphasis
DRAM
Reliability
Clock Recovery
- CRC fail-over
DRAM
DIMM Topology
Fly-by CLK, CMD
FIFO
Buffer
Clock
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Rev. 1.51 January 2008
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