AT24C04D-CUM-T datasheet, PDF - EEWORLD Datasheet

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AT24C04D-CUM-T: DescriptionEEPROM, 512X8, Serial, CMOS, PBGA8, 1.50 X 2 MM, 0.50 MM PITCH, GREEN, VFBGA-8; Categorystorage storage; File Size1MB，27 Pages; ManufacturerAtmel (Microchip)

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AT24C04D-CUM-T Overview

EEPROM, 512X8, Serial, CMOS, PBGA8, 1.50 X 2 MM, 0.50 MM PITCH, GREEN, VFBGA-8

AT24C04D-CUM-T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
package instruction	VFBGA, BGA8,2X4,40/20
Reach Compliance Code	compli
ECCN code	EAR99
Maximum clock frequency (fCLK)	1 MHz
Data retention time - minimum	100
Durability	1000000 Write/Erase Cycles
I2C control byte	1010DDMR
JESD-30 code	R-PBGA-B8
length	2 mm
memory density	4096 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	512 words
character code	512
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512X8
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA8,2X4,40/20
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8/3.3 V
Certification status	Not Qualified
Maximum seat height	0.85 mm
Serial bus type	I2C
Maximum standby current	4e-7 A
Maximum slew rate	0.001 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	1.5 mm
Maximum write cycle time (tWC)	5 ms
write protect	HARDWARE

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AT24C04D

C-Compatible (2-wire) Serial EEPROM

4-Kbit (512 x 8)

PRELIMINARY DATASHEET

Features



Low Voltage Operation

= 1.7V to 3.6V

Internally Organized as 512 x 8 (4K)

C-compatible (2-Wire) Serial Interface

Schmitt Triggers, Filtered Inputs for Noise Suppression

Bidirectional Data Transfer Protocol

400kHz (1.7V) and 1MHz (2.5V) Compatibility

Write Protect Pin For Full Array Hardware Data Protection

Ultra Low Active Current (1mA Max) and Standby Current (0.8μA Max)

16-byte Page Write Mode

Partial Page Writes Allowed

Random and Sequential Read Modes

Self-timed Write Cycle within 5ms Max

High Reliability

Endurance: 1,000,000 Write Cycles

Data Retention: 100 Years

8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP,

(1)

5-lead SOT23,

and 8-ball VFBGA



Green Package Options (Lead-free/Halide-free/RoHS Compliant)



Die Sale Options: Wafer Form and Tape and Reel Available

Description

The Atmel

AT24C04D provides 4,096 bits of Serial Electrically Erasable and

Programmable Read-Only Memory (EEPROM) organized as 512 words of 8 bits

each. The device’s cascadable feature allows up to four devices to share a

common 2-wire bus. This device is optimized for use in many industrial and

commercial applications where low power and low voltage operation are

essential. The device is available in space-saving 8-lead SOIC, 8-lead TSSOP,

8-pad UDFN, 8-lead PDIP,

(1)

5-lead SOT23, and 8-ball VFBGA packages. The

entire family of packages operate from 1.7V to 3.6V.

Note:

Contact Atmel Sales for the availability of this package.

Atmel-8896A-SEEPROM-AT24C04D-Datasheet_032014

Device Operation and Communication

The AT24C04D operates as a slave device and utilizes a simple I2C-compatible 2-wire digital serial interface to

communicate with a host controller, commonly referred to as the bus Master. The Master initiates and controls

all Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices

can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin

is used to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive command

and data information from the Master as well as to send data back to the Master. Data is always latched into the

AT24C04D on the rising edge of SCL and always output from the device on the falling edge of SCL. Both the

SCL and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects

of input spikes and bus noise.

All command and data information is transferred with the Most-Significant Bit (MSB) first. During bus

communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been

transferred, the receiving device must respond with either an acknowledge (ACK) or a no-acknowledge (NACK)

response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master. Therefore, nine clock

cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or

Write operation, so there must not be any interruptions or breaks in the data stream during each data byte

transfer and ACK or NACK clock cycle.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable

while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will

occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master

and the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited

and is determined by the Master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the

logic-high state at the same time.

3.1

Clock and Data Transition Requirements

The SDA pin is an open drain terminal and therefore must be pulled high with an external pull-up resistor. Data

on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will

indicate a Start or Stop condition as defined below.

3.2

3.2.1

Start and Stop Conditions

Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable

Logic 1 state and will bring the device out of standby mode. The Master uses a Start condition to initiate any

data transfer sequence, therefore every command must begin with a Start condition. The device will

continuously monitor the SDA and SCL pins for a Start condition but will not respond unless one is detected.

Please refer to

Figure 3-1

for more details.

3.2.2

Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the

Logic 1 state. The Master can use the Stop condition to end a data transfer sequence with the AT24C04D which

will subsequently return to standby mode. The Master can also utilize a repeated Start condition instead of a

Stop condition to end the current data transfer if the Master will perform another operation. Please refer to

Figure 3-1

for more details.

AT24C04D [PRELIMINARY DATASHEET]

Atmel-8896A-SEEPROM-AT24C04D-Datasheet_032014

3.3

Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the Master that it has successfully

received the data byte by responding with what is known as an acknowledge (ACK). An ACK is accomplished

by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle followed by the

receiving device responding with a Logic 0 during the entire high period of the ninth clock cycle.

When the AT24C04D is transmitting data to the Master, the Master can indicate that it is done receiving data

and wants to end the operation by sending a Logic 1 response to the AT24C04D instead of an ACK response

during the ninth clock cycle. This is known as a no-acknowledge (NACK) and is accomplished by the Master

sending a Logic 1 during the ninth clock cycle, at which point the AT24C04D will release the SDA line so the

Master can then generate a Stop condition.

The transmitting device, which can be the bus Master or the Serial EEPROM, must release the SDA line at the

falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a Logic 0 to ACK the

previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow

the transmitter to continue sending new data. A timing diagram has been provided in

Figure 3-1

to better

illustrate these requirements.

Figure 3-1.

Start Condition, Data Transitions, Stop Condition and Acknowledge

SDA

Must Be

Stable

SDA

Must Be

Stable

Acknowledge Window

SCL

Stop

Condition

SDA

Start

Condition

SDA

Change

Allowed

SDA

Change

Allowed

Acknowledge

Valid

The transmitting device (Master or Slave)

must release the SDA line at this point to allow

the receiving device (Master or Slave) to drive the

SDA line low to ACK the previous 8-bit word.

The receiver (Master or Slave)

must release the SDA line at

this point to allow the transmitter

to continue sending new data.

3.4

Standby Mode

The AT24C04D features a low power standby mode which is enabled when any one of the following occurs:



A valid power-up sequence is performed (see

Section 8.5, “Power-Up Requirements and Reset

Behavior”).

A Stop condition is received by the device unless it initiates an internal write cycle (see

Section 5.).

At the completion of an internal write cycle (see

Section 5., “Write Operations”).

An unsuccessful match of the device type identifier or hardware address in the Device Address byte

occurs (see

Section 4.1, “Device Addressing”).

The bus Master does not ACK the receipt of data read out from the device; instead it sends a NACK

response. (see

Section 6., “Read Operations”).

AT24C04D [PRELIMINARY DATASHEET]

Atmel-8896A-SEEPROM-AT24C04D-Datasheet_032014

AT24C04D-CUM-T Related Products

	AT24C04D-CUM-T	AT24C04D-WWU11M
Description	EEPROM, 512X8, Serial, CMOS, PBGA8, 1.50 X 2 MM, 0.50 MM PITCH, GREEN, VFBGA-8	EEPROM, 512X8, Serial, CMOS, DIE
Maker	Atmel (Microchip)	Atmel (Microchip)
package instruction	VFBGA, BGA8,2X4,40/20	DIE,
Reach Compliance Code	compli	compli
ECCN code	EAR99	EAR99
Maximum clock frequency (fCLK)	1 MHz	1 MHz
JESD-30 code	R-PBGA-B8	R-XUUC-N
memory density	4096 bi	4096 bi
Memory IC Type	EEPROM	EEPROM
memory width	8	8
Number of functions	1	1
word count	512 words	512 words
character code	512	512
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	512X8	512X8
Package body material	PLASTIC/EPOXY	UNSPECIFIED
encapsulated code	VFBGA	DIE
Package shape	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	UNCASED CHIP
Parallel/Serial	SERIAL	SERIAL
Serial bus type	I2C	I2C
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	NO LEAD
Terminal location	BOTTOM	UPPER
Maximum write cycle time (tWC)	5 ms	5 ms

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