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TSPC750AECIP200EE

Description
RISC Microprocessor, 32-Bit, 200MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size210KB,17 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

TSPC750AECIP200EE Overview

RISC Microprocessor, 32-Bit, 200MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288

TSPC750AECIP200EE Parametric

Parameter NameAttribute value
MakerAtmel (Microchip)
Parts packaging codePGA
package instruction,
Contacts288
Reach Compliance Codeunknow
ECCN code3A001.A.2.C
Address bus width32
bit size32
boundary scanYES
External data bus width64
Integrated cacheYES
JESD-30 codeR-XXMA-P288
Number of terminals288
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
speed200 MHz
Maximum supply voltage2.73 V
Minimum supply voltage2.47 V
Nominal supply voltage2.6 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formPIN/PEG
Terminal locationUNSPECIFIED
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC
TSPC750IP
Processor and Cache Module
DESCRIPTION
The Processor and Cache Module (PCM) is a 17 x 17 pin grid
array (PGA) circuit assembly which combines a PowerPCt
microprocessor and SRAM components into a CPU subsys-
tem. The PCM provides a standard mechanical, electrical, and
functional interface which can be socketed on a computer sys-
tem board and allows many combinations of processors and
optional components to be easily interchanged. This docu-
ment describes the general characteristics for a module con-
sisting of a single PowerPCt microprocessor and two SRAM
devices for L2 cache. The PCM packaging and PGA signal
definition also accomodates single processors without SRAM,
and multiple processors.
The PCM consists of an epoxy–glass (FR4) substrate which
adapts a processor in a ceramic ball grid array (CBGA) pac-
kage with 50 mil spacing to a 288–pin PGA with 100 mil spac-
ing that can be easily socketed and hence, easily upgraded.
The FR4 substrate can be extended beyond the area of the 17
x 17 pin grid array to provide an interconnect area for SRAM
components configured as closely coupled L2 cache. The
resulting PCM provides numerous flexible configurations of
processor and cache for various price/performance system
designs.
FR4 PCM on PGA 288 Interposer
I
N
60x Address
T
60x Data
E
R
60x Control
P
O
S
PLL_CFG
E
R
P
I
N
S
TSPC750
Processor
L2 Addr
L2 Data
L2 Control
L2–Cache
Memory
Chips
VID
PID
General
Support
Circuits
Simplified Block Diagram
April 1999
1/17
End soon~~~
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