SSI 32F8030
®
A TDK Group Company
Programmable
Electronic Filter
April 1995
DESCRIPTION
The SSI 32F8030 Programmable Electronic Filter pro-
vides an electronically controlled low–pass filter with a
separate differentiated low–pass output. A seven–
pole, 0.05° Equiripple-type linear phase, low–pass
filter is provided along with a single-pole, single-zero
differentiator. Both outputs have matched delays. The
delay matching is unaffected by any amount of pro-
grammed high frequency peaking (boost) or band-
width. This programability, combined with low group
delay variation makes the SSI 32F8030 ideal for use in
many applications. Double differentiation high fre-
quency boost is accomplished by a two–pole, low–
pass with a two–pole, high–pass feed forward section
to provide complementary real axis zeros. A variable
attenuator is used to program the zero locations, which
controls the amount of boost.
The SSI 32F8030 programmable boost and bandwidth
characteristics can be controlled by external DACs or
DACs provided in the SSI 32D4661 Time Base Gen-
erator. Fixed characteristics are easily accomplished
with three external resistors. In addition, boost can be
switched in or out by a logic signal.
The SSI 32F8030 requires only a +5V supply and is
available in 16-Lead SON, and SOL packages.
FEATURES
•
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•
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Ideal for:
- constant density recording applications
- magnetic tape recording
Programmable filter cutoff frequency
(ƒc = 250 kHz to 2.5 MHz)
Programmable high frequency peaking
(0 to 9 dB boost at the filter cutoff frequency)
Matched normal and differentiated low-pass
outputs
Differential filter input and outputs
±
3.0% group delay variation from
0.2 ƒc to 1.75 ƒc, 0.25 MHz
≤
ƒc
≤
2.5 MHz
Total harmonic distortion less than 1%
+5V only operation
16-Lead SON, and SOL packages
5 mW idle mode
BLOCK DIAGRAM
PIN DIAGRAM
VIN+
VIN-
Low Pass
Filter
Summer
Low Pass
Filter
VO_NORM+
VO_NORM-
GND1
VO_NORM-
VO_NORM+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VO_DIFF+
VO_DIFF-
PWRON
VR
VCC2
IFP
VFP
GND2
High Pass
Filter
Variable
Atten.
High Pass
Filter
VO_DIFF+
VO_DIFF-
VCC1
VIN-
VIN+
VBP
IFP
VFP
FBST
GND1
GND2
VCC1
VCC2
VREF
Filter
Control
BIAS
PWRON
VR
VBP
FBST
CAUTION: Use handling procedures necessary
for a static sensitive component.
04/14/95 - rev.
1
SSI 32F8030
Programmable
Electronic Filter
FUNCTIONAL DESCRIPTION
The SSI 32F8030, a high performance programmable
electronic filter, provides a low pass 0.05° Equiripple-
type linear phase seven pole filter with matched normal
and differentiated outputs. The device has been opti-
mized for usage with several Silicon Systems prod-
ucts, including the SSI 32D4661 Time Base Generator,
the SSI 32P54x family of Pulse Detectors, and the SSI
32P4720 Combo device (Data Separator and Pulse
Detector).
CUTOFF FREQUENCY PROGRAMMING
The SSI 32F8030 programmable electronic filter can
be set to a filter cutoff frequency from 250 kHz to 2.5
MHz (with no boost).
Cutoff frequency programming can be established
using either a current source fed into the IFP pin, whose
output current is proportional to the SSI 32F8030
output reference voltage VR, or by means of an exter-
nal resistor tied from the output voltage reference pin
VR to pin VFP. The former method is optimized using
the SSI 32D4661 Time Base Generator, since the
current source into pin IFP is available at the DAC F
output of the 32D4661. Furthermore, the voltage
reference input is supplied to pin VR3 of the 32D4661
by the reference voltage VR from the VR pin of the
32F8030. This reference voltage is an internally gen-
erated bandgap reference, which typically varies less
than 1 % over voltage supply and temperature varia-
tion. (For the calculations below IVFP = current into IFP
or VFP pins).
The cutoff frequency, determined by the -3dB point
relative to a very low frequency value (< 10kHz), is
related to the current IVFP injected into pin IFP by the
formula
Fc (ideal, in MHz) = 3.125•IFP = 3.125•IVFP•2.2/VR,
where IFP and IVFP are in mA, 0.08<IFP<0.8 mA, and
VR is in volts.
If a current source is used to inject current into pin IFP,
pin VFP should be left open.
If the 32F8030 cutoff frequency is set using voltage VR
to bias up a resistor tied to pin VFP, the cutoff frequency
is related to the resistor value by the formula
Fc (ideal, in MHz) = 3.125•IFP = 3.125•2.2/(3•Rx)
where Rx is in kΩ, & 0.917 kΩ <Rx<9.17 kΩ.
If pin VFP is used to program cutoff frequency, pin IFP
should be left open.
2
SLIMMER HIGH FREQUENCY BOOST
PROGRAMMING
The amplitude of the output signal at frequencies near
the cutoff frequency can be increased using this fea-
ture. Applying an external voltage to pin VBP which is
proportional to reference output voltage VR (provided
by the VR pin) will set the amount of boost. A fixed
amount of boost can be set by an external resistor
divider network connected from pin VBP to pins VR and
GND. No boost is applied if pin FBST, frequency boost
enable, is at a low logic level.
The amount of boost FB at the cutoff frequency Fc is
related to the voltage VBP by the formula
FB (ideal, in dB) = 20 log10[1.884(VBP/VR)+1], where
0<VBP<VR.
SSI 32F8030
Programmable
Electronic Filter
PIN DESCRIPTION
NAME
VIN+, VIN-
VO_NORM+,
VO_NORM-
VO_DIFF+,
VO_DIFF-
IFP
TYPE
I
O
O
O
I
DIFFERENTIAL DIFFERENTIATED OUTPUTS. For minimum time skew,
these outputs should be AC coupled to the pulse detector.
FREQUENCY PROGRAM INPUT. The filter cutoff frequency FC, is set by an
external current IFP, injected into this pin. IFP must be proportional to voltage
VR. This current can be set with an external current generator such as a DAC.
VFP should be left open when using this pin.
FREQUENCY PROGRAM INPUT. The filter cutoff frequency can be set by
programming a current through a resistor from VR to this pin. IFP should be
left open when using this pin.
FREQUENCY BOOST PROGRAM INPUT. The high frequency boost is set
by an external voltage applied to this pin. VBP must be proportional to voltage
VR. A fixed amount of boost can be set by an external resistor divider network
connected from VBP to VR and GND. No boost is applied if the FBST pin is
grounded, or at logic low.
FREQUENCY BOOST. A high logic level or open input enables the frequency
boost circuitry.
POWER ON. A high logic level enables the chip. A low level puts the chip in
a low power state.
REFERENCE VOLTAGE. Internally generated reference voltage.
+5 VOLT SUPPLY.
GROUND
DESCRIPTION
DIFFERENTIAL SIGNAL INPUTS. The input signals must be AC coupled to
these pins.
DIFFERENTIAL NORMAL OUTPUTS. The output signals must be AC
coupled.
VFP
I
VBP
I
FBST
PWRON
VR
VCC1, VCC2
GND1, GND2
I
I
–
I
–
3
SSI 32F8030
Programmable
Electronic Filter
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation above maximum ratings may damage the device.
PARAMETER
Storage Temperature
Junction Operating Temperature, Tj
Supply Voltage, VCC1, VCC2
Voltage Applied to Inputs
IFP, VFP Inputs Maximum Current
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC1, VCC2
Ambient Temperature
4.5 < VCC1,2 < 5.50V
0 < Ta < 70°C
RATING
-65 to +150°C
+130°C
-0.5 to 7V
-0.5 to VCC + 0.5V
≤1.2
mA
4
SSI 32F8030
Programmable
Electronic Filter
Power Supply Characteristics
Unless otherwise specified, recommended operating conditions apply.
PARAMETER
ICC
ICC
PD
PD
Power Supply Current
Power Supply Current
Power Dissipation
Power Dissipation
CONDITIONS
PWRON
≤
0.8V
PWRON
≥
2.0V
PWRON
≥
2.0V
PWRON
≤
0.8V
28
140
MIN
NOM
MAX
0.5
42
231
3
UNIT
mA
mA
mW
mW
DC Characteristics
VIH
VIL
IIH
IIL
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VIH = 2.7V
VIL = 0.4V
–1.5
TTL input
2.0
-0.3
VCC+0.3
0.8
20
V
V
µA
mA
Filter Characteristics
ƒc = 1.25 MHz unless otherwise stated
FCA
AO
AD
TGD0
TGDB
Filter ƒc Accuracy
VO_NORM Diff Gain
VO_DIFF Diff Gain
Group Delay Variation
Without Boost*
Group Delay Variation
With Boost*
using IFP pin: IFP = 0.4 mA or
using VFP pin: Rx = 1.84 kΩ
F = 0.67 ƒc, FB = 0 dB
F = 0.67 ƒc, FB = 0 dB
VBP = VR
0.25 MHz
≤
ƒc
≤
2.5 MHz
F = 0.2 ƒc to 1.75 ƒc
0.25 MHz
≤
ƒc
≤
2.5 MHz
VBP = VR, F = 0.2 ƒc to 1.75 ƒc
THD = 1% max, F = 0.67 ƒc
(no boost, 1000 pF capacitor across Rx)
THD = 1% max, F = 0.67 ƒc
VBP = 0 (1000 pF capacitor across Rx)
THD = 1% max, F = 0.67 ƒc
VBP = VR (1000 pF capacitor across Rx)
THD = 1% max, F = 0.67 ƒc
VBP = 0 (1000 pF capacitor across Rx)
THD = 1% max, F = 0.67 ƒc
VBP = VR (1000 pF capacitor across Rx)
1.125
0.8
0.9AO
8.0
–3
–3
1.0
1.0
1.0
1.0
1.0
9.2
1.375
1.20
1.1AO
10.4
+3
+3
MHz
V/V
V/V
dB
%
%
Vpp
Vpp
Vpp
Vpp
Vpp
FBA Frequency Boost Accuracy
VIF Filter Input Dynamic Range
VOF
VOF
Filter Normal Output
Dynamic Range
Filter Normal Output
Dynamic Range
VOF Filter Differentiated Output
Dynamic Range
VOF Filter Differentiated Output
Dynamic Range
5
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