Features
•
Fast Interleave Cycle Time - 35 ns
•
Continuous Memory Interleaving
•
•
•
•
•
•
•
•
– Unlimited Linear Access Data Output
Dual Voltage Range Operation
– Low Voltage Power Supply Range, 3.0V to 3.6V
or Standard 5V
±
10% Supply Range
Low Power CMOS Operation
– 108 mW max. Active at 25 MHz for V
CC
= 3.6V
– 14.4 mW max. Standby for V
CC
= 3.6V
JEDEC Standard Surface Mount Packages
– 44-Lead PLCC
– 40-Lead VSOP (10 x 14mm)
High Reliability CMOS Technology
– 2,000V ESD Protection
– 200 mA Latchup Immunity
Rapid
™
Programming Algorithm - 50
µ
s/word (typical)
CMOS and TTL Compatible Inputs and Outputs
– JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
1-Megabit
(2 x 32K x 16)
16-Bit Interleaved
Low-Voltage OTP
EPROM
AT27LV1026
Preliminary
Description
The AT27LV1026 is a high performance 16-bit interleaved low-voltage 1,048,576-bit
one-time programmable read only memory (OTP EPROM) organized as 2 x 32K x 16
bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode
operation.
Pin Configurations
Pin Name
A0 - A15
O0 - O15
CS
RD
ALE
PGM
NC
Note:
Function
Addresses
Outputs
Chip Select
Read Strobe
Address Latch Enable
Program Strobe
No Connect
Both GND pins must be
connected.
PLCC Top View
O13 O15 VPP VCC ALE A14
O14 CS GND PGM A15
O12
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
42 40
7
5
3
1
43 41 39
8
38
9
37
36
10
35
11
12
34
33
13
14
32
15
31
16
30
17 19 21 23 25 27 29
18 20 22 24 26 28
2
O2 O0 GND A1 A3
O3 O1 RD A0 A2 A4
6
4
44
VSOP Top View
Type 1
A9
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
A11
A13
A15
PGM
A10
A12
A14
ALE
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
2
40
38
36
34
32
30
28
26
39
37
35
33
31
29
27
25
A8
A6
A4
A2
A0
O0
O2
O4
O6
GND
A7
A5
A3
A1
RD
O1
O3
O5
VCC
VPP
CS
O15
O14
O13 O12
O11 O10
O9 O8
18 17
20 19
24 23
22 21
GND O7
Rev. 0956D–02/98
1
This device is internally architected as two 32K x 16 mem-
ory banks, odd and even. To begin a non-linear access
NLA cycle, (which typically equals a minimum of two linear
access LA cycles), ALE is asserted high and CS is
asserted low. The two internal 15-bit counters store the
address for the odd and even banks and increment alter-
nately during each subsequent linear access LA cycle. The
LA cycle will be terminated when CS is asserted high put-
ting the device in standby mode, or another NLA cycle
starts. The LA cycle can be resumed when CS is asserted
low and ALE stays low. The AT27LV1026 will continuously
output data within each LA cycle which is determined by
the read RD signal. Continuous interleave read operation is
possible as there is no physical limit to the linear access LA
output. When the last address in the array is reached the
counters will wrap around to the first address location and
continue.
For a NLA cycle where A0 = 0 (ALE asserted high, CS
asserted low), both even and odd counters will be loaded
with new address (A1 - A15). Outputs (O0 - O15) from the
even bank will be valid in t
ACCNLA
within the NLA cycle, the
outputs from the odd bank will become valid in t
ACCLA
within
the following LA cycle while the even counter increments
by one to ready the data out for the next LA cycle. The out-
puts will have even or odd data alternating and the
counters increment for the consecutive LA cycles until CS
is asserted high putting the device in standby mode, or a
new NLA cycle begins.
For a NLA cycle where A0 = 1 (ALE asserted high, CS
asserted low), the odd counter will be loaded with the new
address (A1 - A15) while the even counter gets loaded with
the new address+1. Outputs (O0 - O15) from odd bank of
memory will be valid in t
ACCNLA
within the NLA cycle, the
data output from the even bank of memory will become
valid in t
ACCLA
within the following LA cycle while the odd
counter increments by one to ready the data out for the
next LA cycle. The outputs will have data from the odd or
even memory bank alternately and the counters increment
for the following consecutive LA cycles until CS is asserted
high putting the device in standby mode, or a new NLA
cycle begins. When coming out of standby mode, the
device can either enter into a new NLA cycle or resume
where the previous LA operation left off and was termi-
nated by standby mode.
System Considerations
Switching under active conditions may produce transient
voltage excursions. Unless accommodated by the system
design, these transients may exceed data sheet limits,
resulting in device non-conformance. At a minimum, a 0.1
µF
high frequency, low inherent inductance, ceramic
capacitor should be utilized for each device. This capacitor
should be connected between the V
CC
and Ground termi-
nals of the device, as close to the device as possible. Addi-
tionally, to stabilize the supply voltage level on printed cir-
cuit boards with large EPROM arrays, a 4.7
µF
bulk elec-
trolytic capacitor should be utilized, again connected
between the V
CC
and Ground terminals. This capacitor
should be positioned as close as possible to the point
where the power supply is connected to the array.
Operating Table
If A0 = 0 at beginning of NLA cycle:
Consecutive
Cycle
NLA
LA
LA
LA
LA
Standby
LA
LA
+1
-
-
+1
Counter
Even
Address
+1
-
+1
-
Odd
Address
-
+1
-
+1
Outputs
from Even Bank
from Odd Bank
from Even Bank
from Odd Bank
from Even Bank
HiZ
from Odd Band
from Even Bank
If A0 = 1 at beginning of NLA cycle:
Consecutive
Cycle
NLA
LA
LA
LA
LA
Standby
LA
LA
-
+1
+1
-
Counter
Even
Address+1
-
+1
-
+1
Odd
Address
+1
-
+1
-
Outputs
from Odd Bank
from Even Bank
from Odd Bank
from Even Bank
from Odd Bank
HiZ
from Even Bank
from Odd Band
and so on.
and so on.
2
AT27LV1026
AT27LV1026
Block Diagram
RD
ALE
A0
CS
PGM
Logic
CLK_ODD
Address
Input
A
1
-A
1 5
CLK_EVEN
Odd Counter
Even Counter
15
15
32K x 16
Memory
Array
32K x 16
Memory
Array
16
V
CC
GND
V
PP
16
MUX
16
CS
Data Outputs
O
0
-O
1 5
A0
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground .......................................-2.0V to +14.0V
(1)
Note:
V
PP
Supply Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
1.
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is V
CC
+ 0.75V DC which
may overshoot to +7.0V for pulses of less than 20
ns.
3
Embedded System
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