CY7C1356BV25
PRELIMINARY
CY7C1354BV25
256K x 36/512K x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully Registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Common I/O architecture
• Single 2.5V power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA
Packages
•IEEE 1149.1 JTAG-compatible boundary scan
• Burst capability—linear or interleaved burst order
•“ZZ” Sleep Mode option and Stop Clock option
NoBL™ logic, respectively. They are designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1354BV25 and
CY7C1356BV25 are equipped with the advanced No Bus
Latency™ (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1354BV25 and
CY7C1356BV25 are pin compatible and functionally equiv-
alent to ZBT
TM
devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
Write operations are controlled by the Byte Write Selects
(BWS
a
–BWS
d
for CY7C1354BV25 and BWS
a
–BWS
b
for
CY7C1356BV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Functional Description
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous-Pipelined Burst SRAMs with
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE
2
CE
3
WE
BWS
x
Mode
CONTROL
and WRITE
LOGIC
256KX36/
512KX18
MEMORY
ARRAY
OUTPUT
REGISTERS
and LOGIC
D
Data-In REG.
Q
DQ
x
DQP
x
CY7C1354
A
X
DQ
X
DQP
X
BWS
X
X = 17:0
X = a, b, c, d
X = a, b, c, d
X = a, b, c, d
CY7C1356
X = 18:0
X = a, b
X = a, b
X = a, b
OE
Cypress Semiconductor Corporation
Document #: 38-05292 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 15, 2002
CY7C1356BV25
PRELIMINARY
Pin Definitions
Pin Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the address locations.
Sampled at the rising
edge of the CLK.
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
a
controls DQ
a
and DQP
a
, BWS
b
controls DQ
b
and DQP
b
, BWS
c
controls DQ
c
and DQP
c
, BWS
d
controls DQ
d
and
DQP
d
.
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address.
When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
Clock Input.
Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW.
Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Clock Enable Input, active LOW.
When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
Bidirectional Data I/O lines.
As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
[17:0]
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a
–DQ
d
are placed in
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines.
Functionally, these signals are identical to
DQ
[31:0]
. During write sequences, DQP
a
is controlled by BWS
a
, DQP
b
is controlled by
BWS
b
, DQP
c
is controlled by BWS
c
, and DQP
d
is controlled by BWS
d
.
Mode Input.
Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine.
Sampled on the rising edge
of TCK.
Clock input to the JTAG circuitry.
CY7C1354BV25
Input-
Synchronous
Input-
Synchronous
CLK
CE
1
CE
2
CE
3
OE
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQ
a
DQ
b
DQ
c
DQ
d
I/O-
Synchronous
DQP
a
DQP
b
DQP
c
DQP
d
MODE
I/O-
Synchronous
Input
Strap Pin
TDO
TDI
TMS
TCK
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Test Mode Select
Synchronous
JTAG-Clock
Document #: 38-05292 Rev. *A
Page 5 of 25
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