MB9EF226 - Titan
MB9EF226 Series
General Description
MB9EF226 series is based on Cypress’s advanced ARM architecture (32-bit with instruction pipeline for RISC-like performance).
Improvements compared to the previous generation include significantly improved performance at higher frequency, reduced power
consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 128MHz
operation frequency from an external resonator.
Note:
ARM, Cortex, Thumb and CoreSight are the trademarks of ARM Limited in the EU and other countries.
Features
High-Performance/High Memory Content
ARM Cortex R4, 8KB D-Cache, 8KB I-Cache
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32-Bit ARMv7 architecture
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205 DMIPS
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2MB Internal Flash
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48KB Internal EEFlash (Data Flash)
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208KB Internal RAM with ECC
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Secure Hardware Extension (SHE)
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Self-contained secure area
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Random Number generator
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Secure repository for cryptographic keys
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AES encryption/decryption block
Up/Down Counters
Programmable Pulse Generators
Analog-to-Digital Converters - 50 channels
Sound Generator
Free Running/Reload Timers
Real Time Clock (RTC)
Input Capture Units, Output Compare units
32 external Interrupts
Switchable Power Domains
16KB Retention RAM
Flexible Clock Control
Debugging/Testing
ARM Coresight Debug and Trace
Debugging via JTAG Interface
Boundary Scan
5V and 3.3V capable IOs
Ta:
40 °C to +105 °C
Package: LQFP-176
Hybrid Automotive Instruments Cluster with pointers and TFT
display
Classical Automotive Instruments Cluster with pointers
Other Features
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Graphics
2D-Graphics Engine
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1MB Embedded VRAM
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Max Resolution: 1024 pixel hor. x 1024 pixel ver.
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4 Display Layer plus Alpha blending layer
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Display Controller/TCON
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Max. Pixel clock of 40MHz
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Bit Blitter
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Signature Unit
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Command Sequencer
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TTL and RSDS Output (RGB888)
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Dithering for Display with low color resolution
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Low Power
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Connectivity
2x CAN, 2 x LIN-USART, 3 x SPI, 1 x I2C, 2 x I2S
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Up to six Stepper Motor Control (SMC) outputs
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HS-SPI (memory mapped access)
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Characteristics
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Safety Features/Security Features
Multiple Memory Production Units (MPU)
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Peripheral Protection Units (PPU)
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Timing Protection Unit (TPU)
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Cyclic Redundancy Checks (CRC of Flash, Cache and RAM)
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Watchdog
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Flash-, Debug- and Test-Security
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Applications
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Errata:
For information on silicon errata, see
Errata on page 291.
Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 002-05678 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 21, 2017
MB9EF226 - Titan
Block Diagram
Graphical Subsystem "IRIS−SDL "
Display
Controller
GFX0_DCLKI
GFXSPI_CLKi
GFXSPI_DATA0i.... GFXSPI_DATA3i
GFXSPI_SSi
GFX0_DISP[0].... GFX0_DISP[25]
GFX0_TSIG[0].... GFX0_TSIG[11]
DBG0_CTL
DBG0_CLK
DBG0_TRACE0.... DBG0_TRACE7
X0
X1
MODE
X0A
X1A
RSTX
Controlgroup
EIC
NMI
RTC
SYSC
Watchdog
TPU
IRQ Control
Power Control
CLK_CFG_PD1
EIC0_INT00.... EIC0_INT31
Pixel
Engine
TCON
Memories
EIC0_NMI
RTC_WOT
SYSC_CKOT
SYSC_CKOTX
CLK_CFG_PD4
Bus Matrix
Signature
EEFlash
48K option
CLK_MEM_E_PD3
RetRAM
16K
TCMRAM
128K
CLK_MEM_E_PD3
HS−SPI
Command
Seq
SPI−MEM
256MB
VRAM
512KB/1M
CLK_DBG_PD2
Cortex R4
I−Cache
8K
128 MHz
MPU
8 ch
D−Cache
8K
SHE
Clock group
Oscillators
PLL’s
CSV/CLK−out
HS−SPI
(1 ch)
Memory
Map
BootROM
16K
ECC
TCFlash
2M
CLK_HPM_PD2
On−chip
Debug
CLK_TRACE_PD2
SRAM
64K
Trace
CLK_GFX_PD5
CLK_SYS_PD3
High Performance Matrix (HPM)
CLK_HPM_PD2
CLK_HPM_PD2
CLK_DMA_PD2
DMA0_DEOP_ACK0, DMA0_DEOP_ACK1
DMA0_DREQ0, DMA0_DREQ1
DMA0_DSTP0, DMA0_DSTP1
DMA0_DREQ_ACK0, DMA0_DREQ_ACK1
DMA0_DSTP_ACK0, DMA0_DSTP_ACK1
DMA0_DEOP0, DMA0_DEOP1
SPIn_CLKi
SPIn_DATA0i˘. SPIn_DATA3i
SPIn_SSi
SPIn_CLKo
SPIn_DATA[0]o˘. SPIn_DATA[3]o
SPIn_SSo
SPIn_SSO[1]˘. SPIn_SSO[3]
I2Sn_ECLK
I2Sn_SCKi
I2Sn_SDi
I2Sn_WSi
I2Sn_SDo
I2Sn_WSo
I2Sn_SCKo
SG_SGA
SG_SGO
CLK_HPM_PD2
CLK_HPM_PD2
Peripheral Bus
Bridge 3
RLT
(10 ch)
RLTn_TIN
RLTn_TOUT
UDC0_AIN0, UDC0_AIN1
UDC0_BIN0, UDC0_BIN1
UDC0_ZIN0, UDC0_ZIN1
UDC0_UDOT0
UDC0_UDOT1
Peripheral Bus
Bridge 4
DMA
(8 ch)
Peripheral Bus
Bridge 1
PERI5_AHB BUS
Peripheral Bus
Bridge 0
PERI3_eRBUS
PERI4_SLAVE AHB BUS
UDC
(1 ch)
SPI
(3 ch)
SG
(1 ch)
CAN
(2 ch)
USART
(1 ch)
I/O Timer
(4 ch)
FRT 16/17/18/19
ICU 18/19
OCU 16/17
16−bit PPG
(8 ch)
CLK_PERI1_PD2
CLK_PERI0_PD2
10−bit ADC
(50 ch)
I/O Timer
(4 ch)
FRT 0/1/2/3
ICU 2/3
OCU 0/1
USART
(1 ch)
I2C
(1 ch)
SMC
(6 ch)
16−bit PPG
(16 ch)
AVDD5
AVSS5
AVRH
ADC0_AN0..... ADC0_AN31
ADC0_EDGI
GPIOn_mi
PERI1_RBUS
PERI0_RBUS
GPIO
(117 pins)
I2S
(2 ch)
CANn_RX
CANn_TX
USART6_SCKi
USART6_SIN
USART6_SCKo
USART6_SOT
GPIOn_mo
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
USART0_SCKi
USART0_SIN
USART0_SCKo
USART0_SOT
I2C0_SCLi
I2C0_SDAi
I2C0_SCLo
I2C0_SDAo
SMCn_M1
SMCn_P1
SMCn_M2
SMCn_P2
PPG_ETRG0˘.. PPG_ETRG3
PPGn_PPGA
PPGn_PPGB
CLK_PERI3_PD2
PPU
CLK_PERI4_PD2
MLBn_CLKi
CRC
MLB
(1 ch)
MLBn_SIGo
MLBn_DATo
FRTn_FRCK
ICUn_IN0, ICUn_IN1
OTDn,OTDn_I,OTDn_G,OTDn_GI
PPG_ETRG0˘.. PPG_ETRG3
PPGA
PPGB
Power Domain
Power Domain
PD1
PD2
PD4
Modules
Clockgroup (Osc, PLL, CSV), Controlgroup (EIC, NMI, RTC, SYSC, WDG, TPU, IRQ Control, Power Control)
Peripheral bus 0 (ADC, FRT, ICU, OCU, USART, I2C, SMC, PPG), Peripheral bus 1 (SG, CAN, USART, FRT,
ICU, OCU, PPG), Peripheral bus 3 (RLT, UDC, GPIO, PPU), Peripheral bus 4 (SPI, I2S), On-Chip Debug, Trace,
SRAM, CRC, Cortex R4, SHE, MPU, I-Cache, D-Cache, TCM, TCFlash, EEFlash, TPU, BootROM, HS-SPI, MLB,
IRIS-SDL
RetRAM
Document Number: 002-05678 Rev. *B
Page 2 of 320
MB9EF226 - Titan
Contents
MB9EF226 Features ......................................................... 4
Resource Distribution for Non-modulated Clock ....... 13
Lock/Unlock Values for Protection Units ................... 13
ID-Values for Module Identification Registers ........... 14
Package and Pin Assignment ....................................... 15
Package .................................................................... 15
QFP-176 Pin Assignment .......................................... 15
I/O Pins and Functions .............................................. 19
I/O Pin Types ............................................................. 65
IO Circuit Types ......................................................... 68
Packages ................................................................... 73
Interrupt/DMA .................................................................. 74
Interrupt Table ........................................................... 74
NMI ............................................................................ 79
DMA Overview .......................................................... 80
PPU ........................................................................... 84
Master ID ................................................................... 85
I/O Map ............................................................................. 85
Electrical Characteristics ............................................. 244
Absolute Maximum Ratings ..................................... 244
Recommended Operating Conditions ..................... 248
DC Characteristics .................................................. 249
AC Characteristics ................................................... 256
Analog Digital Converter ......................................... 267
FLASH Memory Program/Erase Characteristics ..... 269
RC Oscillator Frequency ......................................... 270
ESD Structure between Power Domains ................ 272
Procedures .................................................................... 274
Boundary Scan ........................................................ 274
Flash Parallel Programming .................................... 276
Debug and Trace ..................................................... 285
Handling Devices .......................................................... 287
Preventing Latch-up ................................................ 287
Handling of Unused Input Pins ................................ 287
Power Supply Pins .................................................. 287
Power on Sequence ................................................ 287
Pin State During Active External Reset ................... 288
Crystal Oscillator Circuit .......................................... 288
Notes on Using External Clock ................................ 288
Reference Documents .................................................. 290
Errata ............................................................................. 291
Ordering Information .................................................... 307
Appendix ....................................................................... 308
Workaround for IRQ Unit Register
Read Timing Issue .................................................. 308
Workaround for Flash Erase
Suspend Internal ..................................................... 314
Workaround for IUNIT Interrupt
Handling Problem .................................................... 315
Limitation Details Undefined Port
Pin State while Core Supply (VDD)
is Unavailable .......................................................... 316
Multiple Analog Switches of SMC
Port Pins in Conducting State ................................. 317
Document History Page ............................................... 319
Sales, Solutions, and Legal Information .................... 320
Worldwide Sales and Design Support ..................... 320
Products .................................................................. 320
PSoC® Solutions .................................................... 320
Cypress Developer Community ............................... 320
Technical Support ................................................... 320
Document Number: 002-05678 Rev. *B
Page 3 of 320
MB9EF226 - Titan
MB9EF226 Features
Table 1. Overview
Feature
Max. Core frequency
DMA
TCFlash
EEFlash
AXI RAM (with ECC)
TCM RAM (with ECC)
RetRAM
Core has 4-way-associative cache
SHE
Boot-ROM
IRQ Ctrl
Graphics subsystem
Graphic RAM (VRAM)
RTC (with auto calibration)
Source clock timer
RLT (Reload Timer) (32 bit)
FRT
ICU
OCU
PPG
SG (Sound Generator)
UDC (UpDown Counter)
CAN
USART (LIN-USART)
SPI
I2C
I2S
Quad - SPI
Media LB
EIC (External Interrupts)
NMI (intern / extern)
SMC
ADC (10-bit)
CRC
Package
MB9EF226 / QFP-176
128 MHz
8 channels
2 MB
48 KB
64 KB
128 KB
16 KB
I/D each 8KB
yes
16 KB
256
Iris-SDL
1MB
1 channel
4
10 channels
8 channels
8 channels
8 channels
24 channels
1 channel
2 channels
2 channels
2 channels
3 channels
1 channel
2 channels
2 channel
1 channel
32 channels
32/1
4(6) channels
50 channels
(including 24 channels shared with SMC)
1 channel
QFP-176
MB9EF226L / QFP-176
128 MHz
8 channels
2 MB
48 KB
64 KB
128 KB
16 KB
I/D each 8KB
yes
16 KB
256
-
1MB
1 channel
4
10 channels
8 channels
8 channels
8 channels
24 channels
1 channel
2 channels
2 channels
2 channels
3 channels
1 channel
2 channels
2 channel
1 channel
32 channels
32/1
4 channels
50 channels
(including 24 channels shared with SMC)
1 channel
QFP-176
Document Number: 002-05678 Rev. *B
Page 4 of 320
MB9EF226 - Titan
Table 2. Device Features
Feature
Technology
90 nm CMOS with embedded flash
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Cortex R4 CPU core
32-bit ARM architecture, dual-issue superscalar eight stage pipeline
ARMv7 and Thumb-2 instruction set compliant
Memory Protection Unit (MPU) with 12 regions
Two Tightly Coupled Memory (TCM) ports. 64-bit AXI slave port for access to TCMs
64-bit AXI master port
Vectored Interrupt Controller (VIC) port for faster interrupt processing
Single error correction, double error detection (SECDED) Error Correction Coding (ECC) for memory error detection and correction
Instruction cache: 8KB 4-way set-associative
Data cache: 8KB 4-way set-associative
Up to 8 break-points and 8 watchpoints
ARM Coresight technology
Standard 5-pin JTAG interface
4-bit, 8-bit and 16-bit trace data width supported depending on package
Secure entry supported for debugger
2D graphics engine with base level hardware acceleration
Maximum frame resolution: 1024 pixel x 1024 pixel
Video modes up to 40MHz pixel clock
1MB embedded SRAM video memory
64-bit multi-layer AXI bus for memory access
Quad SPI interface for external flash
One background and 3 alpha blended foreground layers.
One dedicated alpha layer.
Rotation of display by 90/180/270 degrees
Gamma correction for display output
Color dithering for low resolution panels
Copy and blend bit operations (OpenGL and OpenVG blending modes)
Pixel formats 1, 2, 4, 8, 16, 24, and 32 bpp
Raster operations (ROP2 and ROP3)
External main clock of 4MHz (up to 8MHz under evaluation)
External sub clock (typical 32.768 kHz)
Embedded RC oscillator (typical 8/12 MHz, configurable)
Embedded Slow RC oscillator (typical 100 kHz)
On-chip Phase Locked Loop (PLL) clock multiplier for main clock, Spread Spectrum Clock Generation (SSCG), SSCG for graphics
Stabilization timers for all source clocks
Description
Processor Subsystem
Debug and Trace
Graphics Subsystem
Clocks
Clock Supervisor
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Clock supervision for all source clocks and PLL outputs
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Reset generation for out-of-bound clock frequencies on input source clocks, or PLL output clocks
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External Reset
Software triggered hard reset
Clock supervision resets
Watchdog
Low Voltage Detection reset
Software reset
32-bit counter
Supports selection of four clock sources (Main clock, Sub clock, RC clock or Slow RC clock)
Support for window watchdog functionality
Reset or NMI generation support on watchdog errors
Support for preemptive warning interrupt before watchdog reset or NMI generation
Additional safety provision through three times redundancy and error correction logic for important configuration bits
Option to halt watchdog counter in case of core reaching break-point
Resets
Watchdog Timer
Document Number: 002-05678 Rev. *B
Page 5 of 320
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