PRELIMINARY INFORMATION
ICS7210
L
OW
P
OWER
C
RYSTAL
O
SCILLATOR
Description
The ICS7210 is a low power crystal oscillator that
comes in multiple different offerings for an array of
different frequencies. For normal operation, it only
requires the addition of a crystal. This part exhibits high
stability over wide voltage and temperature ranges.
The ICS7210 also features a disable mode that
switches the output to a high impedance state. This
feature is useful for minimizing power dissipation during
standby and when multiple oscillator circuits are
employed.
The ICS7210 is pin-compatible to the Intersil HA7210.
For other input/output frequencies, please contact an
ICS representative or ICS directly.
Features
•
•
•
•
•
•
•
•
Packaged as 8-pin SOIC
Oscillator replacement
3.3 V or 5 V operating voltage
5µA supply current at 32 kHz
Available in Pb-free packaging
Industrial temperature range (-40° to +85°C)
Pin Compatible to Intersil HA7210
Multiple frequency inputs available:
ICS7210-01.........32.768 kHz
ICS7210-02.........8 MHz
ICS7210-03.........1 MHz
ICS7210-04.........5 MHz
Block Diagram
VDD
Enable
External
Crystal
Oscillator
Output
GND
MDS 7210 A
I n t e gra te d C i r c u i t S y s t e m s
●
1
5 25 Race Stre et, San Jo se, CA 9 5126
●
Revision 092805
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
PRELIMINARY INFORMATION
ICS7210
L
OW
P
OWER
C
RYSTAL
O
SCILLATOR
Pin Assignment
1
2
3
4
8
7
6
5
VDD
X1
X2
GND
Enable
NC
NC
CLK
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDD
X1
X2
GND
CLK
NC
NC
Enable
Pin
Type
Power
Input
Output
Ground
Output
—
—
Input
Pin Description
Connect to +3.3 V or +5 V.
Crystal input connection.
Crystal output connection.
Connect to Ground
CLK output.
No Connect.
No Connect.
Disable mode to switch the output to a high impedance state.
MDS 7210 A
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 092805
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS7210
L
OW
P
OWER
C
RYSTAL
O
SCILLATOR
External Components
The ICS7210 requires a minimum number of external
components for proper operation.
In the equation, C
L
is the crystal load capacitance. So
for a crystal with a 16 pF load capacitance, two 20
pF[(16-6)x2] capacitors should be used
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD (pin 1) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS7210. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50Ω trace (a commonly
used trace impedance) place a 33Ω resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20Ω
.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation crystal caps (pF) = (C
L
-2)x2
MDS 7210 A
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 092805
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
PRELIMINARY INFORMATION
ICS7210
L
OW
P
OWER
C
RYSTAL
O
SCILLATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS7210. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured with respect to
GND)
Power Supply Ramp Time
Min.
-40
+1.6
Typ.
Max.
+85
+3.6
4
Units
°
C
V
ms
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Operating Supply Current
Symbol
VDD
IDD
Conditions
f=32 kHz, C
L
=10 pF, EN=1
f=32 kHz, C
L
=40 pF, EN=1
f=1 MHz, C
L
=10 pF, EN=1
f=1 MHz, C
L
=40 pF, EN=1
Min.
2
Typ.
5
3.6
6.5
90
180
Max.
7
6.1
9
180
270
Units
V
µA
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
IH
V
IL
V
OH
V
OL
C
IN
I
OH
= -12 mA
I
OL
= 12 mA
2
0.8
2.4
0.4
5
V
V
V
pF
MDS 7210 A
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 092805
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
ICS7210
L
OW
P
OWER
C
RYSTAL
O
SCILLATOR
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Clock Duty Cycle
Output Rise Time
Output Fall Time
Power-up Time
Symbol
f
IN
f
OUT
t
1
- t
2
t
3
t
4
t
PU
Conditions
Note 2, Figure 1
At VDD/2, Note 2,
Figures 1 and 2
10% to 90%,
Note 2, Figure 3
10% to 90%,
Note 2, Figure 3
PLL lock-time from
power-up, Figure 4
Min.
Typ.
Max. Units
MHz
MHz
45
50
12
14
55
%
ns
ns
10
2
ms
ms
PDTS goes high until
t
PZH
, t
PZL
stable CLK outputs,
Figure 5
Note 2: Measured with a 15 pF load.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Am-
bient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
MDS 7210 A
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 092805
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
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