ICS87159
1-
TO
-8 LVPECL-
TO
-HCSL
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87159 is a high performance 1-to-8 Differential-to-
HCSL/LVCMOS Clock Generator. The ICS87159 has one
differential input (which can accept LVDS, LVPECL,
LVHSTL, SSTL, HCSL), eight differential HCSL output pairs
and two complementary LVCMOS/LVTTL outputs. The
eight HCSL output pairs can be configured for divide-by-1, 2,
and 4 or high impedance by use of select pins. The two
complementary LVCMOS/LVTTL outputs can be configured
for divide by 2, divide by 4, high impedance, or driven low for
low power operation.
The primary use of the ICS87159 is in *Intel ® E8870
chipsets that use *Intel ® Pentium 4 processors. The
ICS87159 converts the differential clock from the main
system clock into HCSL clocks used by *Intel ® Pentium 4
processors. However, the ICS87159 is a highly flexible,
general purpose device that operates up to 600MHz and
can be used in any situation where Differential-to-HCSL
translation is required.
F
EATURES
•
Eight HCSL outputs
•
Two LVCMOS outputs
•
LVPECL clock input pair
•
PCLK, nPCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 600MHz
•
Output skew: 110ps (maximum)
•
Propagation delay: 3.6ns (maximum)
•
3.3V operating supply
•
0°C to 85°C ambient operating temperature
•
Industrial temperature information available upon request
•
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
MULT_0
MULT_1
IREF
▲
P
IN
A
SSIGNMENT
V
DD
HOST_P2
HOST_N2
GND_H
V
DD
HOST_P7
HOST_N7
GND_H
GND_H
V
DD
_H
GND
V
DD
V
DD
_R
PCLK
nPCLK
GND_R
V
DD
_M
MREF
nMREF
GND_M
V
DD
GND
V
DD
_L
V
DD
GND_L
SEL_T
MULT_0
MULT_1
V
DD
_L
GND_L
SEL_A
SEL_B
SEL_U
PWR_DWN#
V
DD
_H
GND_H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
HOST_P1
HOST_N1
V
DD
GND_H
V
DD
_H
HOST_P2
HOST_N2
GND_H
HOST_P3
HOST_N3
V
DD
_
H
HOST_P4
HOST_N4
GND_H
HOST_P5
HOST_N5
V
DD
_H
HOST_P6
HOST_N6
GND_H
HOST_P7
HOST_N7
V
DD
_H
IREF
GND_I
V
DD
_I
HOST_P8
HOST_N8
CURRENT
ADJUST
-
+
÷1
÷2
÷4
PWR_DWN#
SEL_T
PCLK
nPCLK
÷1
÷2
÷4
SEL_A
SEL_B
SEL_U
DIVIDER
CONTROL
V
DD
HOST_P1
HOST_N1
GND_H
V
DD
HOST_P3
HOST_N3
GND_H
V
DD
HOST_P4
HOST_N4
GND_H
V
DD
HOST_P5
HOST_N5
GND_H
V
DD
HOST_P6
HOST_N6
GND_H
V
DD
HOST_P8
HOST_N8
GND_H
V
DD
MREF
nMREF
GND_H
56-Lead TSSOP
6.1mm x 14.0mm x .92mm body package
G Package
Top View
÷2
÷4
87159AG
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1
REV. B JULY 25, 2010
ICS87159
1-
TO
-8 LVPECL-
TO
-HCSL
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 28, 37,
43, 49, 53
2, 27, 34
40, 46, 52
3, 14
4, 13, 16, 54
5
6
7
8
9
10, 11
12
15
17, 22
18
19
Name
GND_H
V
DD
_H
GND
V
DD
V
DD
_R
PCLK
nPCLK
GND_R
V
DD
_M
MREF, nMREF
GND_M
V
DD
_L
GND_L
SEL_T
MULT_0
Type
Power
Power
Power
Power
Power
Input
Input
Power
Power
Output
Power
Power
Power
Input
Input
Pulldown
Description
Power supply ground for the differential HOST clock outputs.
Positive supply pins for the differential HOST clock outputs.
Power supply ground.
Positive supply pins.
Positive supply pin for LVPECL reference clock inputs.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Power supply ground for LVPECL inputs.
Positive supply pin for MREF clock outputs.
Single ended clocks provided as a reference clock to a memor y clock
driver. LVCMOS / LVTTL clock output.
Power supply ground for MREF clock outputs.
Positive supply pin for logic input pins.
Power supply ground for logic input pins.
Active high input tristates all outputs.
LVCMOS / LVTTL interface levels.
The logic setting on these two pins selects the multiplying factor of the
Pulldown IREF reference current for the HOST pair outputs.
LVCMOS / LVTTL interface levels.
The logic setting on these two pins selects the multiplying factor of the
Pullup IREF reference current for the HOST pair outputs.
LVCMOS / LVTTL interface levels.
Positive supply pin for logic input pins.
Pulldown Selects desired output frequencies. LVCMOS / LVTTL interface levels.
Pullup
Asynchronous active-low LVTTL power-down signal forces MREF
outputs low, tristates HOST_N outputs, and drives HOST_P output
currents to 2xIREF. LVCMOS / LVTTL interface levels.
Differential output pairs. HCSL interface levels.
Positive supply pin for IREF current reference input.
Power supply ground for IREF current reference input.
A fixed precision resistor from this pin to ground provides a reference
current used for differential current-mode HOST clock outputs.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
20
21
23, 24,
25
26
29, 30
31
32
33
35, 36
38, 39
41, 42
44, 45
MULT_1
V
DD
_L
SEL_A, _B,
_U
PWR_DWN#
HOST_N8,
HOST_P8
V
DD
_I
GND_I
IREF
HOST__N7
HOST__P7
HOST_N6,
HOST_P6
HOST__N5,
HOST__P5
HOST _N4,
HOST _P4
Input
Power
Input
Input
Output
Power
Power
Input
Output
Output
Output
Output
continued on next page...
87159AG
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2
REV. B JULY 25, 2010
ICS87159
1-
TO
-8 LVPECL-
TO
-HCSL
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
Number
47, 48
50, 51
55, 56
Name
HOST_N3,
HOST_P3
HOST _N2,
HOST_P2
HOST_N1,
HOST_P1
Type
Output
Output
Output
Description
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
Differential output pairs. HCSL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
LVCMOS Output Impedance
Test Conditions
Minimum
Typical
4
51
51
22
Maximum
Units
pF
kΩ
kΩ
Ω
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Ι½ π υ τσ
ΠΩ Ρ
_ Δ Ω Ν#
1
1
1
1
1
1
1
1
1
0
_Τ
0
0
0
0
0
0
0
0
1
X
_Α
0
0
0
0
1
1
1
1
X
X
_Β
0
0
1
1
0
0
1
1
X
X
_Υ
0
1
0
1
0
1
0
1
X
X
Η_ Π2
Η_ Ν2
÷2
Hi Z
÷4
÷4
÷1
Hi Z
÷2
÷2
Hi Z
H_P1 =
2xIREF
H_N1 =
Hi Z
Η_ Π1
Η_ Ν1
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
H_P2 =
2xIREF
H_N2 =
Hi Z
Η_ Π3
Η_ Ν3
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
H_P3 =
2xIREF
H_N3 =
Hi Z
Η_ Π4
Η_ Ν4
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
H_P4 =
2 x IREF
H_N4
= Hi Z
Ο υ τπ υ τσ
Η_ Π5
Η_ Ν5
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
H_P5 =
2xIREF
H_N5 =
Hi Z
Η_ Π6
Η_ Ν6
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
H_P6 =
2xIREF
H_N6
= Hi Z
Η_ Π8
Η_ Ν8
÷2
÷2
÷2
÷4
÷1
÷1
÷1
÷2
Hi Z
H_P5 =
2xIREF
H_N5
= Hi Z
Η_ Π7
Η_ Ν7
÷2
Hi Z
÷4
÷4
÷1
Hi Z
÷2
÷2
Hi Z
H_P1 =
2xIREF
H_N1
= Hi Z
ΜΡ Ε Φ_ Π
ΜΡ Ε Φ_ Ν
÷4
÷4
÷4
÷4
÷4
÷4
÷4
÷2
Hi Z
MREF_P
= low
MREF_N
= low
T
ABLE
3B. F
UNCTION
T
ABLE
Inputs
MULT_0
0
0
1
1
MULT_1
0
1
0
1
Board Target
Trace/Term Z
50
Ω
50
Ω
50
Ω
50
Ω
Reference R,
IREF = V
DD
/ (3*Rr)
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Rr = 475 1%,
IREF = 2.32mA
Output Current
IOH = 5*IREF
IOH = 6*IREF
IOH = 4*IREF
IOH = 7*IREF
V
OH
@ 50
Ω
environment
0.6
0.7
0.5
0.8
87159AG
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3
REV. B JULY 25, 2010
ICS87159
1-
TO
-8 LVPECL-
TO
-HCSL
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
58.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Operating Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
48
Maximum
3.465
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
MULT_1, PWR_DWN#
Input High Current SEL_A, SEL_B,
SEL_T, SEL_U,
MULT_0
MULT_1, PWR_DWN#
Input Low Current SEL_A, SEL_B,
SEL_T, SEL_U
MULT_0
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
mV
mV
µA
µA
µA
µA
V
V
I
IL
V
OH
Output Low Voltage; NOTE 1
V
OL
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
NOTE 1: Outputs terminated with 50
Ω
to V
DD
/2. See Paramter Measurement Information Section,
"3.3V Output Load Test Circuit".
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK, nPCLK
PCLK, nPCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
Units
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
V
CMR
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is V
DD
+ 0.3V.
87159AG
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4
REV. B JULY 25, 2010
ICS87159
1-
TO
-8 LVPECL-
TO
-HCSL
÷1, ÷2, ÷4 C
LOCK
G
ENERATOR
T
ABLE
4D. HCSL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
I
OH
V
OH
V
OL
I
OZ
V
OX
Parameter
Output Current
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Crossover Voltage
RREF = 475
Ω
, RLOAD = 50
Ω
RREF = 475
Ω
, RLOAD = 50
Ω
-10
280
Test Conditions
Minimum
12.9
0.7
0.03
10
430
Typical
Maximum
14.9
Units
mA
V
V
µA
V
T
ABLE
5A. HCSL AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4, 5
Par t-to-Par t Skew; NOTE 3, 5
Cycle-to-Cycle Jitter
Output Rise/Fall Time
20% to 80%
125
3.0
3.3
65
Test Conditions
Minimum
Typical
Maximum
600
3.6
110
500
150
800
Units
MHz
ns
ps
ps
ps
ps
t
sk(o)
t
sk(pp)
t
jit(cc)
t
R
/ t
F
o dc
Output Duty Cycle
48
52
%
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to HOST_XX outputs only.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: Maximum value calculated at +3
σ
from typical.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. LVCMOS/LVTTL AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay
Cycle-to-Cycle Jitter
Output Rise Time
Output Fall Time
Measured at V
DD
/2
C
L
= 10pF/30pF
0.4V to 2.4V, C
L
= 10pF
0.4V to 2.4V, C
L
= 30pF
0.4V to 2.4V, C
L
= 10pF
0.4V to 2.4V, C
L
= 30pF
0.4
2
52
0.4
1.8
2.85
3.35
Test Conditions
Minimum
Typical
Maximum
300
3.85
150
Units
MHz
ns
ps
ns
ns
ns
ns
%
t
jit(cc)
t
R
t
F
odc
Output Duty Cycle
C
L
= 10pF/30pF
48
All parameters measured at 200MHz in, 100MHz out on HOST_XX and 50MHz out on MREF.
Current adjust set for V
OH
= 0.7V. Measurements refer to MREF outputs only.
87159AG
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5
REV. B JULY 25, 2010
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